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CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; CAT:NONE; SFS:(4636009)(396003)(346002)(136003)(376002)(39850400004)(46966006)(36840700001)(7696005)(478600001)(5660300002)(8676002)(82310400003)(8936002)(86362001)(186003)(70586007)(70206006)(83380400001)(356005)(336012)(81166007)(52536014)(36860700001)(9686003)(55016002)(4326008)(966005)(2906002)(82740400003)(316002)(47076005)(110136005)(53546011)(6506007)(33656002)(54906003)(26005)(357404004); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 May 2021 19:18:04.3201 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: aefc0ce3-6917-412c-a95e-08d912560105 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DB5EUR03FT041.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM6PR08MB4453 Subject: Re: [dpdk-dev] How to disable SVE auto vectorization while using GCC X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" >=20 > > On Fri, Apr 30, 2021 at 5:27 PM fengchengwen > wrote: > > > > > > Hi, ALL > > > We have a question for your help: > > > 1. We have two platforms, both of which are ARM64, one of which > supports > > > both NEON and SVE, the other only support NEON. > > > 2. We want to run on both platforms with a single binary file, and = use the > > > highest vector capability of the corresponding platform whenever > possible. > > > > I see VPP has a similar feature. IMO, it is not present in DPDK. > > Basically, In order to do this. > > - Compile slow-path code(90% of DPDK) with minimal CPU instruction set > > support > > - Have fastpath function compile with different CPU instruction set > > levels -In slowpath, Attach the fastpath function pointer-based on CPU > > instruction-level support. > > > > > > > 3. So we build the DPDK program with -march=3Darmv8-a+sve+crc (GCC > 10.2). > > > However, it is found that invalid instructions occur when the pr= ogram > > > runs on a machine that does not support SVE (pls see below). > > > 4. The problem is caused by the introduction of SVE in GCC automati= c > vector > > > optimization. > > > > > > So Is there a way to disable GCC automatic vector optimization or u= se > only > > > NEON to perform automatic vector optimization? > > > > > > BTW: we already test -fno-tree-vectorize (as link below) but found = no > effect. > > > > > > https://stackoverflow.com/questions/7778174/how-can-i-disable-vector > > > ization-while-using-gcc > > > > > > > > > The GDB output: > > > EAL: Detected 128 lcore(s) > > > EAL: Detected 4 NUMA nodes > > > Option -w, --pci-whitelist is deprecated, use -a, --allow > > > option instead > > > > > > Program received signal SIGILL, Illegal instruction. > > > 0x0000000000671b88 in eal_adjust_config () > > > (gdb) > > > (gdb) where > > > #0 0x0000000000671b88 in eal_adjust_config () > > > #1 0x0000000000682840 in rte_eal_init () > > > #2 0x000000000051c870 in main () > > > (gdb) > > > > > > The disassembly output of eal_adjust_config: > > > 671b7c: f8237a81 str x1, [x20, x3, lsl #3] > > > 671b80: f110001f cmp x0, #0x400 > > > 671b84: 54ffff21 b.ne 671b68 // > b.any > > > 671b88: 043357f5 addvl x21, x19, #-1 > > > 671b8c: 043457e1 addvl x1, x20, #-1 > > > 671b90: 910562b5 add x21, x21, #0x158 > > > 671b94: 04e0e3e0 cntd x0 > > > 671b98: 914012b5 add x21, x21, #0x4, lsl #12 > > > 671b9c: 52800218 mov w24, #0x10 = // #16 > > > 671ba0: 25d8e3e1 ptrue p1.d > > > 671ba4: 25f80fe0 whilelo p0.d, wzr, w24 > > > 671ba8: a5e04020 ld1d {z0.d}, p0/z, [x1, x0, lsl= #3] > > > > > > > > > Best regards. > > > >=20 > Is there a way to use Gcc function multiversioning for this? > https://gcc.gnu.org/onlinedocs/gcc/Function-Multiversioning.html >=20 > Not sure if this is only available on all compiler versions that DPDK cla= ims to > support. It looks like it made into GCC 6 and LLVM 7 It looks like it is not fully support for Arm. For ex: 'target_clones' is n= ot supported or automatic dispatcher does not seem to be supported, we need= to write our own dispatcher. The following code works and should be suffic= ient for DPDK. There is no need to pass SVE flag at the command line for th= e compiler. I do not have a machine with SVE, so the SVE part is not tested= . #include #include __attribute__((target ("arch=3Darmv8-a+crc"))) int foo_neon () { printf ("Neon\n"); return 1; } __attribute__((target ("arch=3Darmv8-a+sve"))) int foo_sve () { printf ("SVE\n"); return 2; } /* * The following code can go into IO function selection in DPDK during * initialization. */ void foo_selector () { static int(*foo)(void); if (!foo) /* The following code can use DPDK wrappers */ foo =3D getauxval(AT_HWCAP) & HWCAP_SVE ? foo_sve : foo_neon; foo (); } int main () { foo_selector(); return 0; }