From: Honnappa Nagarahalli <Honnappa.Nagarahalli@arm.com>
To: Stanislaw Kardach <kda@semihalf.com>
Cc: "dev@dpdk.org" <dev@dpdk.org>,
Frank Zhao <Frank.Zhao@starfivetech.com>,
Sam Grove <sam.grove@sifive.com>,
"mw@semihalf.com" <mw@semihalf.com>,
"upstream@semihalf.com" <upstream@semihalf.com>, nd <nd@arm.com>,
nd <nd@arm.com>
Subject: RE: [PATCH 09/11] test/ring: disable problematic tests for RISC-V
Date: Tue, 10 May 2022 23:28:05 +0000 [thread overview]
Message-ID: <DBAPR08MB58142513D6D06DFFC1FA905E98C99@DBAPR08MB5814.eurprd08.prod.outlook.com> (raw)
In-Reply-To: <20220505173003.3242618-10-kda@semihalf.com>
<snip>
>
> When compiling for RISC-V in debug mode the large amount of inlining in
> test_ring_basic_ex() and test_ring_with_exact_size() (in test_ring.c) leads to
> large loop bodies. This causes 'goto' and 'for' loop PC-relative jumps generated
> by the compiler to go beyond the architecture limitation of +/-1MB offset (the
> 'j <offset>' instruction). This instruction should not be generated by the
> compiler since C language does not limit the maximum distance for 'goto' or
> 'for' loop jumps.
>
> This only happens in the unit test for ring which tries to perform long loops
> with ring enqueue/dequeue and it seems to be caused by excessive
> __rte_always_inline usage. ring perf test compiles just fine under debug.
>
> To work around this, disable the offending tests in debug mode.
Is this still required given you have submitted [1]
[1] http://patches.dpdk.org/project/dpdk/patch/20220510115758.457794-1-kda@semihalf.com/
>
> Signed-off-by: Stanislaw Kardach <kda@semihalf.com>
> Sponsored-by: Frank Zhao <Frank.Zhao@starfivetech.com>
> Sponsored-by: Sam Grove <sam.grove@sifive.com>
> ---
> app/test/test_ring.c | 8 ++++++++
> config/riscv/meson.build | 5 +++++
> doc/guides/rel_notes/release_22_07.rst | 3 ++-
> 3 files changed, 15 insertions(+), 1 deletion(-)
>
> diff --git a/app/test/test_ring.c b/app/test/test_ring.c index
> bde33ab4a1..7d809c147b 100644
> --- a/app/test/test_ring.c
> +++ b/app/test/test_ring.c
> @@ -955,6 +955,7 @@ test_ring_burst_bulk_tests4(unsigned int test_idx)
> return -1;
> }
>
> +#if !defined(RTE_RISCV_WO_DISABLE_RING_TESTS)
> /*
> * Test default, single element, bulk and burst APIs
> */
> @@ -1189,6 +1190,7 @@ test_ring_with_exact_size(void)
> rte_ring_free(exact_sz_r);
> return -1;
> }
> +#endif
>
> static int
> test_ring(void)
> @@ -1200,12 +1202,18 @@ test_ring(void)
> if (test_ring_negative_tests() < 0)
> goto test_fail;
>
> +/* Disable the following tests on RISC-V in debug mode. This is a
> +work-around
> + * GCC bug for RISC-V which fails to generate proper jumps for loops
> +with large
> + * bodies.
> + */
> +#if !defined(RTE_RISCV_WO_DISABLE_RING_TESTS)
> /* Some basic operations */
> if (test_ring_basic_ex() < 0)
> goto test_fail;
>
> if (test_ring_with_exact_size() < 0)
> goto test_fail;
> +#endif
>
> /* Burst and bulk operations with sp/sc, mp/mc and default.
> * The test cases are split into smaller test cases to diff --git
> a/config/riscv/meson.build b/config/riscv/meson.build index
> 0c16c31fc2..50d0b513bf 100644
> --- a/config/riscv/meson.build
> +++ b/config/riscv/meson.build
> @@ -141,3 +141,8 @@ foreach flag: dpdk_flags endforeach message('Using
> machine args: @0@'.format(machine_args))
>
> +# Enable work-around for ring unit tests in debug mode which fail to
> +link # properly due to bad code generation by GCC.
> +if get_option('optimization') == '0' or get_option('optimization') == 'g'
> + add_project_arguments('-DRTE_RISCV_WO_DISABLE_RING_TESTS',
> +language: 'c') endif
> diff --git a/doc/guides/rel_notes/release_22_07.rst
> b/doc/guides/rel_notes/release_22_07.rst
> index 453591e568..4d64b68dfd 100644
> --- a/doc/guides/rel_notes/release_22_07.rst
> +++ b/doc/guides/rel_notes/release_22_07.rst
> @@ -76,7 +76,8 @@ New Features
> * Debug build of ``app/test/dpdk-test`` fails currently on RISC-V due to
> seemingly invalid loop and goto jump code generation by GCC in
> ``test_ring.c`` where extensive inlining increases the code size beyond the
> - capability of the generated instruction (JAL: +/-1MB PC-relative).
> + capability of the generated instruction (JAL: +/-1MB PC-relative). The
> + workaround is to disable ``test_ring_basic_ex()`` and
> ``test_ring_with_exact_size()`` on RISC-V on ``-O0`` or ``-Og``.
>
> * **Updated Intel iavf driver.**
>
> --
> 2.30.2
next prev parent reply other threads:[~2022-05-10 23:28 UTC|newest]
Thread overview: 64+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-05 17:29 [PATCH 00/11] Introduce support for RISC-V architecture Stanislaw Kardach
2022-05-05 17:29 ` [PATCH 01/11] lpm: add a scalar version of lookupx4 function Stanislaw Kardach
2022-05-05 17:29 ` [PATCH 02/11] examples/l3fwd: fix scalar LPM compilation Stanislaw Kardach
2022-05-05 17:39 ` Stephen Hemminger
2022-05-05 17:49 ` Stanisław Kardach
2022-05-05 18:09 ` Stephen Hemminger
2022-05-05 17:29 ` [PATCH 03/11] eal: add initial support for RISC-V architecture Stanislaw Kardach
2022-05-05 17:29 ` [PATCH 04/11] net/ixgbe: enable vector stubs for RISC-V Stanislaw Kardach
2022-05-05 17:29 ` [PATCH 05/11] net/memif: set memfd syscall ID on RISC-V Stanislaw Kardach
2022-05-05 17:29 ` [PATCH 06/11] net/tap: set BPF syscall ID for RISC-V Stanislaw Kardach
2022-05-05 17:29 ` [PATCH 07/11] examples/l3fwd: enable RISC-V operation Stanislaw Kardach
2022-05-05 17:30 ` [PATCH 08/11] test/cpuflags: add test for RISC-V cpu flag Stanislaw Kardach
2022-05-05 17:30 ` [PATCH 09/11] test/ring: disable problematic tests for RISC-V Stanislaw Kardach
2022-05-05 17:35 ` Stephen Hemminger
2022-05-05 17:43 ` Stanisław Kardach
2022-05-05 18:06 ` Stephen Hemminger
2022-05-10 23:28 ` Honnappa Nagarahalli [this message]
2022-05-11 10:07 ` Stanisław Kardach
2022-05-05 17:30 ` [PATCH 10/11] devtools: add RISC-V to test-meson-builds.sh Stanislaw Kardach
2022-05-05 17:30 ` [PATCH 11/11] test/hash: report non HTM numbers for single r/w Stanislaw Kardach
2022-05-06 9:13 ` [PATCH 00/11] Introduce support for RISC-V architecture David Marchand
2022-05-09 12:24 ` Stanisław Kardach
2022-05-09 12:30 ` Thomas Monjalon
2022-05-11 8:09 ` Morten Brørup
2022-05-11 10:28 ` Stanisław Kardach
2022-05-11 11:06 ` Thomas Monjalon
2022-05-09 14:30 ` David Marchand
2022-05-10 11:21 ` Stanisław Kardach
2022-05-10 12:31 ` Thomas Monjalon
2022-05-10 14:00 ` Stanisław Kardach
2022-05-10 14:23 ` Thomas Monjalon
2022-05-10 15:07 ` [PATCH v2 0/8] " Stanislaw Kardach
2022-05-10 15:07 ` [PATCH v2 1/8] eal: add initial " Stanislaw Kardach
2022-05-10 15:07 ` [PATCH v2 2/8] net/ixgbe: enable vector stubs for RISC-V Stanislaw Kardach
2022-05-10 15:07 ` [PATCH v2 3/8] net/memif: set memfd syscall ID on RISC-V Stanislaw Kardach
2022-05-10 15:07 ` [PATCH v2 4/8] net/tap: set BPF syscall ID for RISC-V Stanislaw Kardach
2022-05-10 15:07 ` [PATCH v2 5/8] examples/l3fwd: enable RISC-V operation Stanislaw Kardach
2022-05-10 15:07 ` [PATCH v2 6/8] test/cpuflags: add test for RISC-V cpu flag Stanislaw Kardach
2022-05-10 15:07 ` [PATCH v2 7/8] devtools: add RISC-V to test-meson-builds.sh Stanislaw Kardach
2022-05-10 15:35 ` Stanisław Kardach
2022-05-10 15:07 ` [PATCH v2 8/8] ci: add RISCV64 cross compilation job Stanislaw Kardach
2022-05-10 15:48 ` [PATCH v3 0/8] Introduce support for RISC-V architecture Stanislaw Kardach
2022-05-10 15:48 ` [PATCH v3 1/8] eal: add initial " Stanislaw Kardach
2022-05-13 6:50 ` Heinrich Schuchardt
2022-05-13 8:42 ` Stanisław Kardach
2022-05-13 10:51 ` Heinrich Schuchardt
2022-05-13 11:47 ` Stanisław Kardach
2022-05-13 15:37 ` Stephen Hemminger
2022-05-16 8:00 ` Stanisław Kardach
2022-05-10 15:48 ` [PATCH v3 2/8] net/ixgbe: enable vector stubs for RISC-V Stanislaw Kardach
2022-05-10 15:48 ` [PATCH v3 3/8] net/memif: set memfd syscall ID on RISC-V Stanislaw Kardach
2022-05-10 15:48 ` [PATCH v3 4/8] net/tap: set BPF syscall ID for RISC-V Stanislaw Kardach
2022-05-10 15:48 ` [PATCH v3 5/8] examples/l3fwd: enable RISC-V operation Stanislaw Kardach
2022-05-10 15:48 ` [PATCH v3 6/8] test/cpuflags: add test for RISC-V cpu flag Stanislaw Kardach
2022-05-10 15:48 ` [PATCH v3 7/8] devtools: add RISC-V to test-meson-builds.sh Stanislaw Kardach
2022-05-10 15:48 ` [PATCH v3 8/8] ci: add RISCV64 cross compilation job Stanislaw Kardach
2022-05-12 15:47 ` Aaron Conole
2022-05-12 16:07 ` Stanisław Kardach
2022-05-13 14:33 ` Aaron Conole
2022-05-12 8:04 ` [PATCH 00/11] Introduce support for RISC-V architecture Heinrich Schuchardt
2022-05-12 8:35 ` Stanisław Kardach
2022-05-12 9:46 ` Heinrich Schuchardt
2022-05-12 13:56 ` Stanisław Kardach
2022-05-12 21:06 ` Heinrich Schuchardt
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