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b=Nqa8WakGmI5B0ue8DbYiOU6JgWBmcbxmcXzOz7leLU7Q0u4JP/51whZUhl4atk9Dp++mDIfUIp6YkBqtW242UY6HziHuz9/MxjVyHmhfjUDFkyA4TdtuTIwvF3Adp92fB1U3HEC649yDiS+eAWOMG/f+AFnsTR+5xlhDjnlngz0= Received: from DBAPR08MB5814.eurprd08.prod.outlook.com (2603:10a6:10:1b1::6) by DB7PR08MB3883.eurprd08.prod.outlook.com (2603:10a6:10:76::28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4669.16; Tue, 9 Nov 2021 21:12:05 +0000 Received: from DBAPR08MB5814.eurprd08.prod.outlook.com ([fe80::8501:86ca:a393:17b7]) by DBAPR08MB5814.eurprd08.prod.outlook.com ([fe80::8501:86ca:a393:17b7%9]) with mapi id 15.20.4690.015; Tue, 9 Nov 2021 21:12:05 +0000 From: Honnappa Nagarahalli To: Joyce Kong , "thomas@monjalon.net" , "david.marchand@redhat.com" , Ruifeng Wang , "konstantin.ananyev@intel.com" , "rsanford@akamai.com" , "erik.g.carrillo@intel.com" , "olivier.matz@6wind.com" , "yipeng1.wang@intel.com" , "sameh.gobriel@intel.com" , "bruce.richardson@intel.com" , "vladimir.medvedkin@intel.com" , "anatoly.burakov@intel.com" , "andrew.rybchenko@oktetlabs.ru" , "jerinj@marvell.com" , "declan.doherty@intel.com" , "ciara.power@intel.com" , "xiaoyun.li@intel.com" , "nicolas.chautru@intel.com" , "maryam.tahhan@intel.com" , "reshma.pattan@intel.com" , "cristian.dumitrescu@intel.com" CC: "dev@dpdk.org" , nd , Honnappa Nagarahalli , nd Thread-Topic: [PATCH v1 04/12] test/stack_perf: use compiler atomics for lcore sync Thread-Index: AQHXh4gTLxCy1X9anECnqh6NILbQ/av8TZBg Date: Tue, 9 Nov 2021 21:12:05 +0000 Message-ID: References: <20210802101847.3462-1-joyce.kong@arm.com> <20210802101847.3462-5-joyce.kong@arm.com> In-Reply-To: <20210802101847.3462-5-joyce.kong@arm.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ts-tracking-id: 0AA9164FC50F6C498B3943739E3FCDF4.0 x-checkrecipientchecked: true Authentication-Results-Original: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com; 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CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; CAT:NONE; SFS:(4636009)(36840700001)(46966006)(5660300002)(4326008)(8676002)(36860700001)(2906002)(508600001)(336012)(316002)(8936002)(52536014)(54906003)(86362001)(70206006)(70586007)(82310400003)(110136005)(81166007)(7696005)(33656002)(921005)(26005)(356005)(55016002)(186003)(9686003)(6506007)(83380400001)(47076005); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Nov 2021 21:12:19.6565 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bfa94fc1-a5c3-4670-bf6b-08d9a3c59d9a X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: VE1EUR03FT049.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB9PR08MB6538 Subject: Re: [dpdk-dev] [PATCH v1 04/12] test/stack_perf: use compiler atomics for lcore sync X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" >=20 > Convert rte_atomic usages to compiler atomic built-ins for lcore sync in > stack_perf test cases. >=20 > Signed-off-by: Joyce Kong > Reviewed-by: Ruifeng Wang Looks good Reviewed-by: Honnappa Nagarahalli > --- > app/test/test_stack_perf.c | 14 ++++++-------- > 1 file changed, 6 insertions(+), 8 deletions(-) >=20 > diff --git a/app/test/test_stack_perf.c b/app/test/test_stack_perf.c inde= x > 4ee40d5d19..1eae00a334 100644 > --- a/app/test/test_stack_perf.c > +++ b/app/test/test_stack_perf.c > @@ -6,7 +6,6 @@ > #include > #include >=20 > -#include > #include > #include > #include > @@ -24,7 +23,7 @@ > */ > static volatile unsigned int bulk_sizes[] =3D {8, MAX_BURST}; >=20 > -static rte_atomic32_t lcore_barrier; > +static uint32_t lcore_barrier; >=20 > struct lcore_pair { > unsigned int c1; > @@ -144,9 +143,8 @@ bulk_push_pop(void *p) > s =3D args->s; > size =3D args->sz; >=20 > - rte_atomic32_sub(&lcore_barrier, 1); > - while (rte_atomic32_read(&lcore_barrier) !=3D 0) > - rte_pause(); > + __atomic_fetch_sub(&lcore_barrier, 1, __ATOMIC_RELAXED); > + rte_wait_until_equal_32(&lcore_barrier, 0, __ATOMIC_RELAXED); >=20 > uint64_t start =3D rte_rdtsc(); >=20 > @@ -175,7 +173,7 @@ run_on_core_pair(struct lcore_pair *cores, struct > rte_stack *s, > unsigned int i; >=20 > for (i =3D 0; i < RTE_DIM(bulk_sizes); i++) { > - rte_atomic32_set(&lcore_barrier, 2); > + __atomic_store_n(&lcore_barrier, 2, __ATOMIC_RELAXED); >=20 > args[0].sz =3D args[1].sz =3D bulk_sizes[i]; > args[0].s =3D args[1].s =3D s; > @@ -208,7 +206,7 @@ run_on_n_cores(struct rte_stack *s, lcore_function_t > fn, int n) > int cnt =3D 0; > double avg; >=20 > - rte_atomic32_set(&lcore_barrier, n); > + __atomic_store_n(&lcore_barrier, n, __ATOMIC_RELAXED); >=20 > RTE_LCORE_FOREACH_WORKER(lcore_id) { > if (++cnt >=3D n) > @@ -302,7 +300,7 @@ __test_stack_perf(uint32_t flags) > struct lcore_pair cores; > struct rte_stack *s; >=20 > - rte_atomic32_init(&lcore_barrier); > + __atomic_store_n(&lcore_barrier, 0, __ATOMIC_RELAXED); >=20 > s =3D rte_stack_create(STACK_NAME, STACK_SIZE, rte_socket_id(), > flags); > if (s =3D=3D NULL) { > -- > 2.17.1