From: Honnappa Nagarahalli <Honnappa.Nagarahalli@arm.com>
To: "Morten Brørup" <mb@smartsharesystems.com>,
"Konstantin Ananyev" <konstantin.v.ananyev@yandex.ru>,
"dev@dpdk.org" <dev@dpdk.org>,
"Bruce Richardson" <bruce.richardson@intel.com>
Cc: Jan Viktorin <viktorin@rehivetech.com>,
Ruifeng Wang <Ruifeng.Wang@arm.com>,
David Christensen <drc@linux.vnet.ibm.com>,
Stanislaw Kardach <kda@semihalf.com>, nd <nd@arm.com>,
nd <nd@arm.com>
Subject: RE: [RFC v2] non-temporal memcpy
Date: Wed, 27 Jul 2022 19:52:51 +0000 [thread overview]
Message-ID: <DBAPR08MB581463646BF2BFD575B23C5D98979@DBAPR08MB5814.eurprd08.prod.outlook.com> (raw)
In-Reply-To: <98CBD80474FA8B44BF855DF32C47DC35D871FD@smartserver.smartshare.dk>
<snip>
>
> > From: Honnappa Nagarahalli [mailto:Honnappa.Nagarahalli@arm.com]
> > Sent: Wednesday, 27 July 2022 19.38
> >
>
> [...]
>
> > >
> > > > > Yes, x86 needs 16B alignment for NT load/stores But that's
> > supposed
> > > > to be arch
> > > > > specific limitation, that we probably want to hide, no?
> > >
> > > Correct. However, optional hints for optimization purposes will be
> > available.
> > > And it is up to the architecture specific implementation to make the
> > best use
> > > of these hints, or just ignore them.
> > >
> > > > > Inside the function can check alignment of both src and dst and
> > > > decide should it
> > > > > use NT load/store instructions or just do normal copy.
> > > > IMO, the normal copy should not be done by this API under any
> > > > conditions. Why not let the application call memcpy/rte_memcpy
> > > > when the NT copy is not applicable? It helps the programmer to
> > understand
> > > > and debug the issues much easier.
> > >
> > > Yes, the programmer must choose between normal memcpy() and non-
> > > temporal rte_memcpy_nt(). I am offering new functions, not modifying
> > > memcpy() or rte_memcpy().
> > >
> > > And rte_memcpy_nt() will silently fall back to normal memcpy() if
> > non-
> > > temporal copying is unavailable, e.g. on POWER and RISC-V
> > architectures,
> > > which don't have NT load/store instructions.
> > I am talking about a scenario where the application is being ported
> > between architectures. Not everyone knows about the capabilities of
> > the architecture. It is better to indicate upfront (ex: compilation
> > failures) that a certain feature is not supported on the target
> > architecture rather than the user having to discover through painful
> > debugging.
>
> I'm considering rte_memcpy_nt() a performance optimized variant of
> memcpy(), where the performance gain is less cache pollution. Thus, silent
> fallback to memcpy() should suffice.
>
> Other architecture differences also affect DPDK performance; the inability to
> perform non-temporal load/store just one more to the (undocumented) list.
>
> Failing at build time if NT load/store is unavailable by the architecture would
> prevent the function from being used by other DPDK libraries, e.g. by the
> rte_pktmbuf_copy() function used by the pdump library.
The other libraries in DPDK need to provide NT versions as the libraries need to cater for not-NT use cases as well. i.e. we cannot hide a NT copy under rte_pktmbuf_copy() API, we need to have rte_pktmbuf_copy_nt()
>
> I don't oppose to your idea, I just don't have any idea how to reasonably
> implement it. So I'm trying to defend why it is not important.
I am suggesting that the applications could implement #ifdef depending on the architecture.
next prev parent reply other threads:[~2022-07-27 19:53 UTC|newest]
Thread overview: 57+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-19 15:26 Morten Brørup
2022-07-19 18:00 ` David Christensen
2022-07-19 18:41 ` Morten Brørup
2022-07-19 18:51 ` Stanisław Kardach
2022-07-19 22:15 ` Morten Brørup
2022-07-21 23:19 ` Konstantin Ananyev
2022-07-22 10:44 ` Morten Brørup
2022-07-24 13:35 ` Konstantin Ananyev
2022-07-24 22:18 ` Morten Brørup
2022-07-29 10:00 ` Konstantin Ananyev
2022-07-29 10:46 ` Morten Brørup
2022-07-29 11:50 ` Konstantin Ananyev
2022-07-29 17:17 ` Morten Brørup
2022-07-29 22:00 ` Konstantin Ananyev
2022-07-30 9:51 ` Morten Brørup
2022-08-02 9:05 ` Konstantin Ananyev
2022-07-29 12:13 ` Konstantin Ananyev
2022-07-29 16:05 ` Stephen Hemminger
2022-07-29 17:29 ` Morten Brørup
2022-08-07 20:40 ` Mattias Rönnblom
2022-08-09 9:24 ` Morten Brørup
2022-08-09 11:53 ` Mattias Rönnblom
2022-10-09 16:16 ` Morten Brørup
2022-07-29 18:13 ` Morten Brørup
2022-07-29 19:49 ` Konstantin Ananyev
2022-07-29 20:26 ` Morten Brørup
2022-07-29 21:34 ` Konstantin Ananyev
2022-08-07 20:20 ` Mattias Rönnblom
2022-08-09 9:34 ` Morten Brørup
2022-08-09 11:56 ` Mattias Rönnblom
2022-08-10 21:05 ` Honnappa Nagarahalli
2022-08-11 11:50 ` Mattias Rönnblom
2022-08-11 16:26 ` Honnappa Nagarahalli
2022-07-25 1:17 ` Honnappa Nagarahalli
2022-07-27 10:26 ` Morten Brørup
2022-07-27 17:37 ` Honnappa Nagarahalli
2022-07-27 18:49 ` Morten Brørup
2022-07-27 19:12 ` Stephen Hemminger
2022-07-28 9:00 ` Morten Brørup
2022-07-27 19:52 ` Honnappa Nagarahalli [this message]
2022-07-27 22:02 ` Stanisław Kardach
2022-07-28 10:51 ` Morten Brørup
2022-07-29 9:21 ` Konstantin Ananyev
2022-08-07 20:25 ` Mattias Rönnblom
2022-08-09 9:46 ` Morten Brørup
2022-08-09 12:05 ` Mattias Rönnblom
2022-08-09 15:00 ` Morten Brørup
2022-08-10 11:47 ` Mattias Rönnblom
2022-08-09 15:26 ` Stephen Hemminger
2022-08-09 17:24 ` Morten Brørup
2022-08-10 11:59 ` Mattias Rönnblom
2022-08-10 12:12 ` Morten Brørup
2022-08-10 11:55 ` Mattias Rönnblom
2022-08-10 12:18 ` Morten Brørup
2022-08-10 21:20 ` Honnappa Nagarahalli
2022-08-11 11:53 ` Mattias Rönnblom
2022-08-11 22:24 ` Honnappa Nagarahalli
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