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CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; CAT:NONE; SFS:(4636009)(39860400002)(136003)(376002)(346002)(396003)(46966005)(5660300002)(82740400003)(47076004)(81166007)(54906003)(4326008)(2906002)(26005)(6506007)(86362001)(8936002)(55016002)(478600001)(70586007)(9686003)(316002)(336012)(186003)(82310400003)(110136005)(52536014)(83380400001)(966005)(356005)(7696005)(33656002)(70206006); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Sep 2020 03:24:08.6597 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9c0d034c-6e77-496d-770a-08d856cb4f98 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DB5EUR03FT048.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR0801MB2063 Subject: Re: [dpdk-dev] [PATCH 1/2] config: add Graviton2(arm64) meson configuration X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" +Jerin, Hemant, Dharmik Hi Vimal, Few comments inline. >=20 > Add meson build configuration for Graviton2 platform with 64-bit ARM > Neoverse N1 cores. This patch makes the following changes to generic > Neoverse N1 config: >=20 > 1. increase lcore limit to 64 > 2. increase memory support to 1TB There will be multiple SoCs with N1 cores. All of them will have the same i= mplementor ID and part number. But, they will have different values for the= se configurable parameters. IMO, from usage perspective, we have 2 cases: 1) Ability to build a portable binary that can run on multiple Arm SoCs (fo= r ex: BlueField, thunderx1, thunderx2, N1SDP, Graviton2 etc) 2) Ability to build a binary which would run only on a SoC it was compiled = for and provide the most optimized binary for that SoC. But, this may not b= e portable. For 1) we have default march. For 2) we do not have the capability today in meson build (at least, this i= s my understanding, please correct me if I am wrong). In this case, the use= r knows the target platform for compilation. IMO, we should add the capabil= ity to take the target platform as an input from the user (similar to the m= ake build system) and Graviton2 can be one such target platform. > 3. remove +crc from -march as that is default when setting armv8.2 >=20 > For more information about Graviton2 platform, refer to: > https://aws.amazon.com/ec2/graviton/ >=20 > Signed-off-by: Vimal Chungath > --- > config/arm/arm64_graviton2_linux_gcc | 17 +++++++++++++++++ > config/arm/meson.build | 12 +++++++++++- > 2 files changed, 28 insertions(+), 1 deletion(-) create mode 100644 > config/arm/arm64_graviton2_linux_gcc >=20 > diff --git a/config/arm/arm64_graviton2_linux_gcc > b/config/arm/arm64_graviton2_linux_gcc > new file mode 100644 > index 000000000..022e06303 > --- /dev/null > +++ b/config/arm/arm64_graviton2_linux_gcc > @@ -0,0 +1,17 @@ > +[binaries] > +c =3D 'aarch64-linux-gnu-gcc' > +cpp =3D 'aarch64-linux-gnu-cpp' > +ar =3D 'aarch64-linux-gnu-gcc-ar' > +strip =3D 'aarch64-linux-gnu-strip' > +pkgconfig =3D 'aarch64-linux-gnu-pkg-config' > +pcap-config =3D '' > + > +[host_machine] > +system =3D 'linux' > +cpu_family =3D 'aarch64' > +cpu =3D 'armv8-a' > +endian =3D 'little' > + > +[properties] > +implementor_id =3D '0x41' > +implementor_pn =3D '0xd0c' > diff --git a/config/arm/meson.build b/config/arm/meson.build index > 8728051d5..64e277ebc 100644 > --- a/config/arm/meson.build > +++ b/config/arm/meson.build > @@ -86,6 +86,16 @@ flags_octeontx2_extra =3D [ > ['RTE_ARM_FEATURE_ATOMICS', true], > ['RTE_EAL_IGB_UIO', false], > ['RTE_USE_C11_MEM_MODEL', true]] > +flags_n1generic_extra =3D [ > + ['RTE_MACHINE', '"neoverse-n1"'], > + ['RTE_MAX_LCORE', 64], > + ['RTE_CACHE_LINE_SIZE', 64], > + ['RTE_ARM_FEATURE_ATOMICS', true], > + ['RTE_USE_C11_MEM_MODEL', true], > + ['RTE_MAX_MEM_MB', 1048576], > + ['RTE_MAX_NUMA_NODES', 1], > + ['RTE_EAL_NUMA_AWARE_HUGEPAGES', false], > + ['RTE_LIBRTE_VHOST_NUMA', false]] >=20 > machine_args_generic =3D [ > ['default', ['-march=3Darmv8-a+crc']], > @@ -97,7 +107,7 @@ machine_args_generic =3D [ > ['0xd09', ['-mcpu=3Dcortex-a73']], > ['0xd0a', ['-mcpu=3Dcortex-a75']], > ['0xd0b', ['-mcpu=3Dcortex-a76']], > - ['0xd0c', ['-march=3Darmv8.2-a+crc+crypto', '-mcpu=3Dneoverse-n1'], > flags_n1sdp_extra]] > + ['0xd0c', ['-march=3Darmv8.2-a+crypto', '-mcpu=3Dneoverse-n1'], > +flags_n1generic_extra]] >=20 > machine_args_cavium =3D [ > ['default', ['-march=3Darmv8-a+crc+crypto','-mcpu=3Dthunderx']], > -- > 2.16.6