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From: Honnappa Nagarahalli <Honnappa.Nagarahalli@arm.com>
To: Ruifeng Wang <Ruifeng.Wang@arm.com>, "jerinj@marvell.com"
<jerinj@marvell.com>, Ruifeng Wang <Ruifeng.Wang@arm.com>, David Marchand
<david.marchand@redhat.com>, Phil Yang <Phil.Yang@arm.com>
CC: "dev@dpdk.org" <dev@dpdk.org>, nd <nd@arm.com>, "stable@dpdk.org"
<stable@dpdk.org>, Honnappa Nagarahalli <Honnappa.Nagarahalli@arm.com>, nd
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Thread-Topic: [PATCH v1] eal/arm: fix clang build of native target
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Subject: Re: [dpdk-dev] [PATCH v1] eal/arm: fix clang build of native target
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<snip>
>=20
> When doing Clang build with '-mcpu=3Dnative' on N1 platform, build failed
> with:
> ../lib/librte_eal/arm/include/rte_atomic_64.h:76:39:
> error: instruction requires: lse
> __ATOMIC128_CAS_OP(__cas_128_release, "caspl")
>=20
> This is because native detection for Neoverse N1 was added in Clang-11.
> Prior version of Clang's assembler doesn't know LSE support on hardware.
> Fixed this for Clang earlier than version 11 by specifying architecture f=
or
> assembler.
> Referred to [1] for this fix.
>=20
> Fixes: 7e2c3e17fe2c ("eal/arm64: add 128-bit atomic compare exchange")
> Cc: stable@dpdk.org
>=20
> [1]
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit=
/?i
> d=3De0d5896bd356cd577f9710a02d7a474cdf58426b
>=20
> Signed-off-by: Ruifeng Wang <ruifeng.wang@arm.com>
Reviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
> ---
> lib/librte_eal/arm/include/rte_atomic_64.h | 4 ++++
> 1 file changed, 4 insertions(+)
>=20
> diff --git a/lib/librte_eal/arm/include/rte_atomic_64.h
> b/lib/librte_eal/arm/include/rte_atomic_64.h
> index 2cef88629..7fcd17466 100644
> --- a/lib/librte_eal/arm/include/rte_atomic_64.h
> +++ b/lib/librte_eal/arm/include/rte_atomic_64.h
> @@ -46,6 +46,8 @@ rte_atomic_thread_fence(int memorder)
> /*------------------------ 128 bit atomic operations -------------------=
------*/
>=20
> #if defined(__ARM_FEATURE_ATOMICS) ||
> defined(RTE_ARM_FEATURE_ATOMICS)
> +#define __LSE_PREAMBLE ".arch armv8-a+lse\n"
> +
> #define __ATOMIC128_CAS_OP(cas_op_name, op_string) =
\
> static __rte_noinline rte_int128_t =
\
> cas_op_name(rte_int128_t *dst, rte_int128_t old, rte_int128_t updated)
> \
> @@ -59,6 +61,7 @@ cas_op_name(rte_int128_t *dst, rte_int128_t old,
> rte_int128_t updated) \
> register uint64_t x2 __asm("x2") =3D (uint64_t)updated.val[0]; \
> register uint64_t x3 __asm("x3") =3D (uint64_t)updated.val[1]; \
> asm volatile( \
> + __LSE_PREAMBLE
> \
> op_string " %[old0], %[old1], %[upd0], %[upd1], [%[dst]]" \
> : [old0] "+r" (x0), \
> [old1] "+r" (x1) \
> @@ -76,6 +79,7 @@ __ATOMIC128_CAS_OP(__cas_128_acquire, "caspa")
> __ATOMIC128_CAS_OP(__cas_128_release, "caspl")
> __ATOMIC128_CAS_OP(__cas_128_acq_rel, "caspal")
>=20
> +#undef __LSE_PREAMBLE
> #undef __ATOMIC128_CAS_OP
>=20
> #endif
> --
> 2.20.1