From: "Kavanagh, Mark B" <mark.b.kavanagh@intel.com>
To: "Richardson, Bruce" <bruce.richardson@intel.com>
Cc: "dev@dpdk.org" <dev@dpdk.org>
Subject: Re: [dpdk-dev] Minimum Supported x86 microarchitecture
Date: Wed, 15 Apr 2015 16:09:23 +0000 [thread overview]
Message-ID: <DC5AD7FA266D86499789B1BCAEC715F846DA65AA@irsmsx105.ger.corp.intel.com> (raw)
In-Reply-To: <20150415160527.GA9836@bricha3-MOBL3>
>-----Original Message-----
>From: Richardson, Bruce
>Sent: Wednesday, April 15, 2015 5:05 PM
>To: Kavanagh, Mark B
>Cc: dev@dpdk.org
>Subject: Re: [dpdk-dev] Minimum Supported x86 microarchitecture
>
>On Wed, Apr 15, 2015 at 03:09:39PM +0000, Kavanagh, Mark B wrote:
>> Hi,
>>
>> The recent reimplementation of rte_memcpy in DPDK v2.0.0 seems to have a placed an
>implicit floor on the microarchitecture/Instruction set supported by DPDK.
>>
>> For example, I can't compile head of OVS against DPDK 2.0 with gcc without passing the
>'msse3' flag; this points to an implicit minimum supported CPU of 'core2'. More
>discussion on same is available here: http://openvswitch.org/pipermail/dev/2015-
>April/053523.html
>>
>> Can anyone confirm or deny this, and is/should it be documented?
>>
>> Thanks in advance,
>> Mark
>
>SSE3 is the minimum necessary. However, I believe all x86_64 cpus have at least
>SSE3 support, so this should only be a problem with 32-bit builds. Is this the
>case for you?
>
>/Bruce
Hey Bruce,
No, I'm compiling on an IVB system.
prev parent reply other threads:[~2015-04-15 16:09 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-04-15 15:09 Kavanagh, Mark B
2015-04-15 16:05 ` Bruce Richardson
2015-04-15 16:09 ` Kavanagh, Mark B [this message]
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