From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by dpdk.org (Postfix) with ESMTP id 8EE02AD92 for ; Wed, 4 Feb 2015 02:55:32 +0100 (CET) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP; 03 Feb 2015 17:50:51 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.09,516,1418112000"; d="scan'208";a="672361752" Received: from pgsmsx103.gar.corp.intel.com ([10.221.44.82]) by fmsmga002.fm.intel.com with ESMTP; 03 Feb 2015 17:55:29 -0800 Received: from shsmsx101.ccr.corp.intel.com (10.239.4.153) by PGSMSX103.gar.corp.intel.com (10.221.44.82) with Microsoft SMTP Server (TLS) id 14.3.195.1; Wed, 4 Feb 2015 09:55:26 +0800 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.161]) by SHSMSX101.ccr.corp.intel.com ([169.254.1.253]) with mapi id 14.03.0195.001; Wed, 4 Feb 2015 09:55:25 +0800 From: "Zhou, Danny" To: Stephen Hemminger Thread-Topic: [dpdk-dev] [PATCH v2 0/5] Interrupt mode for PMD Thread-Index: AQHQQArGjp9eCvREyk2AgKtZp1lpX5zft8EQ Date: Wed, 4 Feb 2015 01:55:25 +0000 Message-ID: References: <1422951511-28143-1-git-send-email-danny.zhou@intel.com> <20150203154012.7ef2495a@urahara> In-Reply-To: <20150203154012.7ef2495a@urahara> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Cc: "dev@dpdk.org" Subject: Re: [dpdk-dev] [PATCH v2 0/5] Interrupt mode for PMD X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 04 Feb 2015 01:55:33 -0000 > -----Original Message----- > From: Stephen Hemminger [mailto:stephen@networkplumber.org] > Sent: Wednesday, February 04, 2015 7:40 AM > To: Zhou, Danny > Cc: dev@dpdk.org > Subject: Re: [dpdk-dev] [PATCH v2 0/5] Interrupt mode for PMD >=20 > On Tue, 3 Feb 2015 16:18:26 +0800 > Zhou Danny wrote: >=20 > > 2) UIO only supports a single interrupt vector which has to been shared= by > > LSC interrupt and interrupts assigned to dedicated rx queues. >=20 > UIO uses msi-x and there is no fundamental reason it could not use one IR= Q for > LSC and one IRQ per queue. Might require some more work in base kernel > but not that hard. Ideally, the uio kernel module before kernel 3.6 (VFIO is supported in kern= els=20 3.6 and greater) needs to be back-ported to support multiple interrupt vect= ors. Yes, it is not hard while it is user responsibility.=20 As for multiplexing that single interrupt vectors, it needs to read up to t= wo=20 MMIO registers to determine what the real interrupt cause it, at the cost of longer latency.=20