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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: DM3PPF7D18F34A1.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 6653f057-e9d5-45d9-5e34-08ddd4f7f681 X-MS-Exchange-CrossTenant-originalarrivaltime: 06 Aug 2025 14:46:01.3657 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: r8SjdUgJGcHgSFfgjLn6nhxP1OfvpjJvU/l5mYPpqh7WreGdX1PrYyjvHGjG3xxtOUK1zUdUCZtG0mJabWJPlA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA3PR11MB9205 X-OriginatorOrg: intel.com X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org >=20 > On Fri, Jul 25, 2025 at 12:49:11PM +0000, Ciara Loftus wrote: > > Use the new function for determining the maximum simd bitwidth in > > the ice driver. > > > > Signed-off-by: Ciara Loftus >=20 > Few comments inline below. > > --- > > drivers/net/intel/ice/ice_ethdev.h | 5 +-- > > drivers/net/intel/ice/ice_rxtx.c | 52 ++++++------------------ > > drivers/net/intel/ice/ice_rxtx.h | 1 + > > drivers/net/intel/ice/ice_rxtx_vec_sse.c | 6 +++ > > 4 files changed, 21 insertions(+), 43 deletions(-) > > > > diff --git a/drivers/net/intel/ice/ice_ethdev.h > b/drivers/net/intel/ice/ice_ethdev.h > > index 5fda814f06..992fcc9175 100644 > > --- a/drivers/net/intel/ice/ice_ethdev.h > > +++ b/drivers/net/intel/ice/ice_ethdev.h > > @@ -11,6 +11,7 @@ > > > > #include > > #include > > +#include > > > > #include "base/ice_common.h" > > #include "base/ice_adminq_cmd.h" > > @@ -674,9 +675,7 @@ struct ice_adapter { > > /* Set bit if the engine is disabled */ > > unsigned long disabled_engine_mask; > > struct ice_parser *psr; > > - /* used only on X86, zero on other Archs */ > > - bool tx_use_avx2; > > - bool tx_use_avx512; > > + enum rte_vect_max_simd tx_simd_width; > > bool rx_vec_offload_support; > > }; > > > > diff --git a/drivers/net/intel/ice/ice_rxtx.c b/drivers/net/intel/ice/i= ce_rxtx.c > > index 85832d95a3..79217249b9 100644 > > --- a/drivers/net/intel/ice/ice_rxtx.c > > +++ b/drivers/net/intel/ice/ice_rxtx.c > > @@ -3703,7 +3703,7 @@ ice_set_rx_function(struct rte_eth_dev *dev) > > struct ci_rx_queue *rxq; > > int i; > > int rx_check_ret =3D -1; > > - bool rx_use_avx512 =3D false, rx_use_avx2 =3D false; > > + enum rte_vect_max_simd rx_simd_width =3D > RTE_VECT_SIMD_DISABLED; > > > > rx_check_ret =3D ice_rx_vec_dev_check(dev); > > if (ad->ptp_ena) > > @@ -3720,35 +3720,22 @@ ice_set_rx_function(struct rte_eth_dev *dev) > > break; > > } > > } > > + rx_simd_width =3D ice_get_max_simd_bitwidth(); > > >=20 > Since this whole block is in #ifdef X86_64, do we need a generic ice > function here? Is it worth just just calling the x86 function directly? We'd then need to include the rx_vec_x86.h file in the common rxtx.c code w= hich I think is probably not desired. We could move the function to rx.h but then that file would have some arch = specific stuff which again is probably not ideal either. >=20 > > - if (rte_vect_get_max_simd_bitwidth() >=3D > RTE_VECT_SIMD_512 && > > - > rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) =3D=3D 1 && > > - > rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) =3D=3D 1) > > -#ifdef CC_AVX512_SUPPORT > > - rx_use_avx512 =3D true; > > -#else > > - PMD_DRV_LOG(NOTICE, > > - "AVX512 is not supported in build env"); > > -#endif > > - if (!rx_use_avx512 && > > - > (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) =3D=3D 1 || > > - > rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) =3D=3D 1) && > > - rte_vect_get_max_simd_bitwidth() >=3D > RTE_VECT_SIMD_256) > > - rx_use_avx2 =3D true; > > } else { > > ad->rx_vec_allowed =3D false; > > } > > > > if (ad->rx_vec_allowed) { > > if (dev->data->scattered_rx) { > > - if (rx_use_avx512) { > > + if (rx_simd_width =3D=3D RTE_VECT_SIMD_512) { > > #ifdef CC_AVX512_SUPPORT > > if (ad->rx_vec_offload_support) > > ad->rx_func_type =3D > ICE_RX_AVX512_SCATTERED_OFFLOAD; > > else > > ad->rx_func_type =3D > ICE_RX_AVX512_SCATTERED; > > #endif > > - } else if (rx_use_avx2) { > > + } else if (rx_simd_width =3D=3D RTE_VECT_SIMD_256) { > > if (ad->rx_vec_offload_support) > > ad->rx_func_type =3D > ICE_RX_AVX2_SCATTERED_OFFLOAD; > > else > > @@ -3757,14 +3744,14 @@ ice_set_rx_function(struct rte_eth_dev *dev) > > ad->rx_func_type =3D ICE_RX_SSE_SCATTERED; > > } > > } else { > > - if (rx_use_avx512) { > > + if (rx_simd_width =3D=3D RTE_VECT_SIMD_512) { > > #ifdef CC_AVX512_SUPPORT > > if (ad->rx_vec_offload_support) > > ad->rx_func_type =3D > ICE_RX_AVX512_OFFLOAD; > > else > > ad->rx_func_type =3D ICE_RX_AVX512; > > #endif > > - } else if (rx_use_avx2) { > > + } else if (rx_simd_width =3D=3D RTE_VECT_SIMD_256) { > > if (ad->rx_vec_offload_support) > > ad->rx_func_type =3D > ICE_RX_AVX2_OFFLOAD; > > else > > @@ -4032,29 +4019,14 @@ ice_set_tx_function(struct rte_eth_dev *dev) > > int tx_check_ret =3D -1; > > > > if (rte_eal_process_type() =3D=3D RTE_PROC_PRIMARY) { > > - ad->tx_use_avx2 =3D false; > > - ad->tx_use_avx512 =3D false; > > + ad->tx_simd_width =3D RTE_VECT_SIMD_DISABLED; > > tx_check_ret =3D ice_tx_vec_dev_check(dev); > > + ad->tx_simd_width =3D ice_get_max_simd_bitwidth(); > > if (tx_check_ret >=3D 0 && > > rte_vect_get_max_simd_bitwidth() >=3D > RTE_VECT_SIMD_128) { > > ad->tx_vec_allowed =3D true; > > > > - if (rte_vect_get_max_simd_bitwidth() >=3D > RTE_VECT_SIMD_512 && > > - rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) > =3D=3D 1 && > > - > rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) =3D=3D 1) > > -#ifdef CC_AVX512_SUPPORT > > - ad->tx_use_avx512 =3D true; > > -#else > > - PMD_DRV_LOG(NOTICE, > > - "AVX512 is not supported in build env"); > > -#endif > > - if (!ad->tx_use_avx512 && > > - > (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) =3D=3D 1 || > > - > rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) =3D=3D 1) && > > - rte_vect_get_max_simd_bitwidth() >=3D > RTE_VECT_SIMD_256) > > - ad->tx_use_avx2 =3D true; > > - > > - if (!ad->tx_use_avx2 && !ad->tx_use_avx512 && > > + if (ad->tx_simd_width < RTE_VECT_SIMD_256 && > > tx_check_ret =3D=3D > ICE_VECTOR_OFFLOAD_PATH) > > ad->tx_vec_allowed =3D false; > > > > @@ -4074,7 +4046,7 @@ ice_set_tx_function(struct rte_eth_dev *dev) > > > > if (ad->tx_vec_allowed) { > > dev->tx_pkt_prepare =3D NULL; > > - if (ad->tx_use_avx512) { > > + if (ad->tx_simd_width =3D=3D RTE_VECT_SIMD_512) { > > #ifdef CC_AVX512_SUPPORT > > if (tx_check_ret =3D=3D ICE_VECTOR_OFFLOAD_PATH) { > > PMD_DRV_LOG(NOTICE, > > @@ -4100,9 +4072,9 @@ ice_set_tx_function(struct rte_eth_dev *dev) > > dev->tx_pkt_prepare =3D ice_prep_pkts; > > } else { > > PMD_DRV_LOG(DEBUG, "Using %sVector Tx > (port %d).", > > - ad->tx_use_avx2 ? "avx2 " : "", > > + ad->tx_simd_width =3D=3D > RTE_VECT_SIMD_256 ? "avx2 " : "", > > dev->data->port_id); > > - dev->tx_pkt_burst =3D ad->tx_use_avx2 ? > > + dev->tx_pkt_burst =3D ad->tx_simd_width =3D=3D > RTE_VECT_SIMD_256 ? > > ice_xmit_pkts_vec_avx2 : > > ice_xmit_pkts_vec; > > } > > diff --git a/drivers/net/intel/ice/ice_rxtx.h b/drivers/net/intel/ice/i= ce_rxtx.h > > index 0301d05888..8c3d6c413a 100644 > > --- a/drivers/net/intel/ice/ice_rxtx.h > > +++ b/drivers/net/intel/ice/ice_rxtx.h > > @@ -261,6 +261,7 @@ uint16_t ice_xmit_pkts_vec_avx512_offload(void > *tx_queue, > > int ice_fdir_programming(struct ice_pf *pf, struct ice_fltr_desc *fdir= _desc); > > int ice_tx_done_cleanup(void *txq, uint32_t free_cnt); > > int ice_get_monitor_addr(void *rx_queue, struct rte_power_monitor_cond > *pmc); > > +enum rte_vect_max_simd ice_get_max_simd_bitwidth(void); > > > > #define FDIR_PARSING_ENABLE_PER_QUEUE(ad, on) do { \ > > int i; \ > > diff --git a/drivers/net/intel/ice/ice_rxtx_vec_sse.c > b/drivers/net/intel/ice/ice_rxtx_vec_sse.c > > index d818b3b728..1545bc3b6e 100644 > > --- a/drivers/net/intel/ice/ice_rxtx_vec_sse.c > > +++ b/drivers/net/intel/ice/ice_rxtx_vec_sse.c > > @@ -735,3 +735,9 @@ ice_tx_vec_dev_check(struct rte_eth_dev *dev) > > { > > return ice_tx_vec_dev_check_default(dev); > > } > > + > > +enum rte_vect_max_simd > > +ice_get_max_simd_bitwidth(void) > > +{ > > + return ci_get_x86_max_simd_bitwidth(); > > +} >=20 > If we do wrap the x86 bitwidth function in an ice-specific one, we probab= ly > need to provide one for other architectures. However, as I comment above,= I > don't think we need to wrap this - though perhaps I'm missing something o= r > its needed in later patches... >=20 > > -- > > 2.34.1 > >