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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: DM4PR11MB5994.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: e4429e32-3b1e-4dfc-c074-08db470eb05d X-MS-Exchange-CrossTenant-originalarrivaltime: 27 Apr 2023 11:01:01.6886 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: f7AofnPoov6KjMtHRQYpUlmdBby01RfE9Nl4p2jv4drZkvYcAFO20isi2MxeTA07gVtCT30K9LQBkt4798tN6g== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR11MB6383 X-OriginatorOrg: intel.com X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org > -----Original Message----- > From: Min Zhou > Sent: Wednesday, April 12, 2023 6:02 PM > To: Yang, Qiming ; Wu, Wenjun1 > ; zhoumin@loongson.cn > Cc: dev@dpdk.org; maobibo@loongson.cn > Subject: [PATCH] net/ixgbe: consider DCB/VMDq conf when getting RSS conf >=20 > The mrqe field of MRQC register is an enum. From the Intel 82599 datashee= t, > we know that these values below for the mrqe field are all related to RSS > configuration: > 0000b =3D RSS disabled. > 0001b =3D RSS only -- Single set of RSS 16 queues. > 0010b =3D DCB enabled and RSS disabled -- 8 TCs, each allocated 1 > queue. > 0011b =3D DCB enabled and RSS disabled -- 4 TCs, each allocated 1 > queue. > 0100b =3D DCB and RSS -- 8 TCs, each allocated 16 RSS queues. > 0101b =3D DCB and RSS -- 4 TCs, each allocated 16 RSS queues. > 1000b =3D Virtualization only -- 64 pools, no RSS, each pool allocated > 2 queues. > 1010b =3D Virtualization and RSS -- 32 pools, each allocated 4 RSS > queues. > 1011b =3D Virtualization and RSS -- 64 pools, each allocated 2 RSS > queues. >=20 > The ixgbe pmd will check whether the rss is enabled or not when getting r= ss > conf. So, beside comparing the value of mrqe field with xxx0b and xxx1b, = we > also needto consider the other configurations, such as DCB + RSS or VMDQ = + > RSS. Otherwise, we may not get the correct rss conf in some cases, such a= s > when we use DCB and RSS with 8 TCs which corresponds to 0100b for the > mrqe field. >=20 > Signed-off-by: Min Zhou > --- > drivers/net/ixgbe/ixgbe_rxtx.c | 91 ++++++++++++++++++++++++++++++---- > 1 file changed, 80 insertions(+), 11 deletions(-) >=20 > diff --git a/drivers/net/ixgbe/ixgbe_rxtx.c b/drivers/net/ixgbe/ixgbe_rxt= x.c > index c9d6ca9efe..1eff0053ed 100644 > --- a/drivers/net/ixgbe/ixgbe_rxtx.c > +++ b/drivers/net/ixgbe/ixgbe_rxtx.c > @@ -3461,18 +3461,89 @@ static uint8_t rss_intel_key[40] =3D { > 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA, }; >=20 > +/* > + * This function removes the rss configuration in the mrqe field of > +MRQC > + * register and tries to maintain other configurations in the field, > +such > + * DCB and Virtualization. > + * > + * The MRQC register supplied in section 7.1.2.8.3 of the Intel 82599 > datasheet. > + * From the datasheet, we know that the mrqe field is an enum. So, > +masking the > + * mrqe field with '~IXGBE_MRQC_RSSEN' may not completely disable rss > + * configuration. For example, the value of mrqe is equal to 0101b when > +DCB and > + * RSS with 4 TCs configured, however 'mrqe &=3D ~0x01' is equal to 0100= b > +which > + * corresponds to DCB and RSS with 8 TCs. > + */ > +static void > +ixgbe_mrqc_rss_remove(struct ixgbe_hw *hw) { > + uint32_t mrqc; > + uint32_t mrqc_reg; > + uint32_t mrqe_val; > + > + mrqc_reg =3D ixgbe_mrqc_reg_get(hw->mac.type); > + mrqc =3D IXGBE_READ_REG(hw, mrqc_reg); > + mrqe_val =3D mrqc & IXGBE_MRQC_MRQE_MASK; > + > + switch (mrqe_val) { > + case IXGBE_MRQC_RSSEN: > + /* Completely disable rss */ > + mrqe_val =3D 0; > + break; > + case IXGBE_MRQC_RTRSS8TCEN: > + mrqe_val =3D IXGBE_MRQC_RT8TCEN; > + break; > + case IXGBE_MRQC_RTRSS4TCEN: > + mrqe_val =3D IXGBE_MRQC_RT4TCEN; > + break; > + case IXGBE_MRQC_VMDQRSS64EN: > + /* FIXME. Can 32 pools with rss convert to 64 pools without rss? */ > + case IXGBE_MRQC_VMDQRSS32EN: better not change the pool number, can we just print a warning and break? Otherwise Acked-by: Qi Zhang