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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: DM4PR11MB5994.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 5ad258c0-05ce-49ff-105c-08dbb4c49a59 X-MS-Exchange-CrossTenant-originalarrivaltime: 14 Sep 2023 01:47:49.9156 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: H6nUht2P/fP5Cny4IDvSSgWcmEeU8pQqL/Y5MESyw0PsxlKmHMmCeTnylo8yqIuZM060P95Gaf0MudICek0qgg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR11MB6572 X-OriginatorOrg: intel.com X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org > -----Original Message----- > From: Zhang, Qi Z > Sent: Wednesday, September 13, 2023 3:46 PM > To: Wu, Wenjun1 ; Su, Simei ; > Wu, Jingjing ; Xing, Beilei > Cc: dev@dpdk.org > Subject: RE: [PATCH v3] common/idpf: refactor single queue Tx function >=20 >=20 >=20 > > -----Original Message----- > > From: Wu, Wenjun1 > > Sent: Wednesday, September 13, 2023 1:57 PM > > To: Su, Simei ; Wu, Jingjing > > ; Xing, Beilei ; Zhang, > > Qi Z > > Cc: dev@dpdk.org > > Subject: RE: [PATCH v3] common/idpf: refactor single queue Tx function > > > > > > > > > -----Original Message----- > > > From: Su, Simei > > > Sent: Friday, September 8, 2023 6:28 PM > > > To: Wu, Jingjing ; Xing, Beilei > > > ; Zhang, Qi Z > > > Cc: dev@dpdk.org; Wu, Wenjun1 ; Su, Simei > > > > > > Subject: [PATCH v3] common/idpf: refactor single queue Tx function > > > > > > This patch replaces flex Tx descriptor with base Tx descriptor to > > > align with kernel driver practice. > > > > > > Signed-off-by: Simei Su > > > --- > > > v3: > > > * Change context TSO descriptor from base mode to flex mode. > > > > > > v2: > > > * Refine commit title and commit log. > > > * Remove redundant definition. > > > * Modify base mode context TSO descriptor. > > > > > > drivers/common/idpf/idpf_common_rxtx.c | 39 +++++++++--------= -- > > > drivers/common/idpf/idpf_common_rxtx.h | 2 +- > > > drivers/common/idpf/idpf_common_rxtx_avx512.c | 37 +++++++++-------- > - > > > drivers/net/idpf/idpf_rxtx.c | 2 +- > > > 4 files changed, 39 insertions(+), 41 deletions(-) > > > > > > diff --git a/drivers/common/idpf/idpf_common_rxtx.c > > > b/drivers/common/idpf/idpf_common_rxtx.c > > > index fc87e3e243..e6d2486272 100644 > > > --- a/drivers/common/idpf/idpf_common_rxtx.c > > > +++ b/drivers/common/idpf/idpf_common_rxtx.c > > > @@ -276,14 +276,14 @@ idpf_qc_single_tx_queue_reset(struct > > > idpf_tx_queue *txq) > > > } > > > > > > txe =3D txq->sw_ring; > > > - size =3D sizeof(struct idpf_flex_tx_desc) * txq->nb_tx_desc; > > > + size =3D sizeof(struct idpf_base_tx_desc) * txq->nb_tx_desc; > > > for (i =3D 0; i < size; i++) > > > ((volatile char *)txq->tx_ring)[i] =3D 0; > > > > > > prev =3D (uint16_t)(txq->nb_tx_desc - 1); > > > for (i =3D 0; i < txq->nb_tx_desc; i++) { > > > - txq->tx_ring[i].qw1.cmd_dtype =3D > > > - > > > rte_cpu_to_le_16(IDPF_TX_DESC_DTYPE_DESC_DONE); > > > + txq->tx_ring[i].qw1 =3D > > > + > > > rte_cpu_to_le_64(IDPF_TX_DESC_DTYPE_DESC_DONE); > > > txe[i].mbuf =3D NULL; > > > txe[i].last_id =3D i; > > > txe[prev].next_id =3D i; > > > @@ -1307,17 +1307,16 @@ idpf_xmit_cleanup(struct idpf_tx_queue > *txq) > > > uint16_t nb_tx_to_clean; > > > uint16_t i; > > > > > > - volatile struct idpf_flex_tx_desc *txd =3D txq->tx_ring; > > > + volatile struct idpf_base_tx_desc *txd =3D txq->tx_ring; > > > > > > desc_to_clean_to =3D (uint16_t)(last_desc_cleaned + txq->rs_thresh)= ; > > > if (desc_to_clean_to >=3D nb_tx_desc) > > > desc_to_clean_to =3D (uint16_t)(desc_to_clean_to - > > nb_tx_desc); > > > > > > desc_to_clean_to =3D sw_ring[desc_to_clean_to].last_id; > > > - /* In the writeback Tx desccriptor, the only significant fields are= the 4- > > > bit DTYPE */ > > > - if ((txd[desc_to_clean_to].qw1.cmd_dtype & > > > - rte_cpu_to_le_16(IDPF_TXD_QW1_DTYPE_M)) !=3D > > > - rte_cpu_to_le_16(IDPF_TX_DESC_DTYPE_DESC_DONE)) { > > > + if ((txd[desc_to_clean_to].qw1 & > > > + rte_cpu_to_le_64(IDPF_TXD_QW1_DTYPE_M)) !=3D > > > + rte_cpu_to_le_64(IDPF_TX_DESC_DTYPE_DESC_DONE)) { > > > TX_LOG(DEBUG, "TX descriptor %4u is not done " > > > "(port=3D%d queue=3D%d)", desc_to_clean_to, > > > txq->port_id, txq->queue_id); @@ -1331,10 +1330,7 @@ > > > idpf_xmit_cleanup(struct idpf_tx_queue *txq) > > > nb_tx_to_clean =3D (uint16_t)(desc_to_clean_to - > > > last_desc_cleaned); > > > > > > - txd[desc_to_clean_to].qw1.cmd_dtype =3D 0; > > > - txd[desc_to_clean_to].qw1.buf_size =3D 0; > > > - for (i =3D 0; i < RTE_DIM(txd[desc_to_clean_to].qw1.flex.raw); i++) > > > - txd[desc_to_clean_to].qw1.flex.raw[i] =3D 0; > > > + txd[desc_to_clean_to].qw1 =3D 0; > > > > > > txq->last_desc_cleaned =3D desc_to_clean_to; > > > txq->nb_free =3D (uint16_t)(txq->nb_free + nb_tx_to_clean); @@ - > > > 1347,8 +1343,8 @@ uint16_t idpf_dp_singleq_xmit_pkts(void > > > *tx_queue, struct rte_mbuf **tx_pkts, > > > uint16_t nb_pkts) > > > { > > > - volatile struct idpf_flex_tx_desc *txd; > > > - volatile struct idpf_flex_tx_desc *txr; > > > + volatile struct idpf_base_tx_desc *txd; > > > + volatile struct idpf_base_tx_desc *txr; > > > union idpf_tx_offload tx_offload =3D {0}; > > > struct idpf_tx_entry *txe, *txn; > > > struct idpf_tx_entry *sw_ring; > > > @@ -1356,6 +1352,7 @@ idpf_dp_singleq_xmit_pkts(void *tx_queue, > > struct > > > rte_mbuf **tx_pkts, > > > struct rte_mbuf *tx_pkt; > > > struct rte_mbuf *m_seg; > > > uint64_t buf_dma_addr; > > > + uint32_t td_offset; > > > uint64_t ol_flags; > > > uint16_t tx_last; > > > uint16_t nb_used; > > > @@ -1382,6 +1379,7 @@ idpf_dp_singleq_xmit_pkts(void *tx_queue, > > struct > > > rte_mbuf **tx_pkts, > > > > > > for (nb_tx =3D 0; nb_tx < nb_pkts; nb_tx++) { > > > td_cmd =3D 0; > > > + td_offset =3D 0; > > > > > > tx_pkt =3D *tx_pkts++; > > > RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf); > > > @@ -1462,9 +1460,10 @@ idpf_dp_singleq_xmit_pkts(void *tx_queue, > > > struct rte_mbuf **tx_pkts, > > > slen =3D m_seg->data_len; > > > buf_dma_addr =3D rte_mbuf_data_iova(m_seg); > > > txd->buf_addr =3D rte_cpu_to_le_64(buf_dma_addr); > > > - txd->qw1.buf_size =3D slen; > > > - txd->qw1.cmd_dtype =3D > > > rte_cpu_to_le_16(IDPF_TX_DESC_DTYPE_FLEX_DATA << > > > - > > > IDPF_FLEX_TXD_QW1_DTYPE_S); > > > + txd->qw1 =3D > > > rte_cpu_to_le_64(IDPF_TX_DESC_DTYPE_DATA | > > > + ((uint64_t)td_cmd << > > > IDPF_TXD_QW1_CMD_S) | > > > + ((uint64_t)td_offset << > > > IDPF_TXD_QW1_OFFSET_S) | > > > + ((uint64_t)slen << > > > IDPF_TXD_QW1_TX_BUF_SZ_S)); > > > > > > txe->last_id =3D tx_last; > > > tx_id =3D txe->next_id; > > > @@ -1473,7 +1472,7 @@ idpf_dp_singleq_xmit_pkts(void *tx_queue, > > struct > > > rte_mbuf **tx_pkts, > > > } while (m_seg); > > > > > > /* The last packet data descriptor needs End Of Packet (EOP) > > */ > > > - td_cmd |=3D IDPF_TX_FLEX_DESC_CMD_EOP; > > > + td_cmd |=3D IDPF_TX_DESC_CMD_EOP; > > > txq->nb_used =3D (uint16_t)(txq->nb_used + nb_used); > > > txq->nb_free =3D (uint16_t)(txq->nb_free - nb_used); > > > > > > @@ -1482,7 +1481,7 @@ idpf_dp_singleq_xmit_pkts(void *tx_queue, > > struct > > > rte_mbuf **tx_pkts, > > > "%4u (port=3D%d queue=3D%d)", > > > tx_last, txq->port_id, txq->queue_id); > > > > > > - td_cmd |=3D IDPF_TX_FLEX_DESC_CMD_RS; > > > + td_cmd |=3D IDPF_TX_DESC_CMD_RS; > > > > > > /* Update txq RS bit counters */ > > > txq->nb_used =3D 0; > > > @@ -1491,7 +1490,7 @@ idpf_dp_singleq_xmit_pkts(void *tx_queue, > > struct > > > rte_mbuf **tx_pkts, > > > if (ol_flags & IDPF_TX_CKSUM_OFFLOAD_MASK) > > > td_cmd |=3D IDPF_TX_FLEX_DESC_CMD_CS_EN; > > > > > > - txd->qw1.cmd_dtype |=3D rte_cpu_to_le_16(td_cmd << > > > IDPF_FLEX_TXD_QW1_CMD_S); > > > + txd->qw1 |=3D rte_cpu_to_le_16(td_cmd << > > > IDPF_TXD_QW1_CMD_S); > > > } > > > > > > end_of_tx: > > > diff --git a/drivers/common/idpf/idpf_common_rxtx.h > > > b/drivers/common/idpf/idpf_common_rxtx.h > > > index 6cb83fc0a6..b49b1ed737 100644 > > > --- a/drivers/common/idpf/idpf_common_rxtx.h > > > +++ b/drivers/common/idpf/idpf_common_rxtx.h > > > @@ -157,7 +157,7 @@ struct idpf_tx_entry { > > > /* Structure associated with each TX queue. */ struct idpf_tx_queue= { > > > const struct rte_memzone *mz; /* memzone for Tx ring */ > > > - volatile struct idpf_flex_tx_desc *tx_ring; /* Tx ring virtual > > > address */ > > > + volatile struct idpf_base_tx_desc *tx_ring; /* Tx ring virtual > > > address */ > > > volatile union { > > > struct idpf_flex_tx_sched_desc *desc_ring; > > > struct idpf_splitq_tx_compl_desc *compl_ring; diff --git > > > a/drivers/common/idpf/idpf_common_rxtx_avx512.c > > > b/drivers/common/idpf/idpf_common_rxtx_avx512.c > > > index 81312617cc..afb0014a13 100644 > > > --- a/drivers/common/idpf/idpf_common_rxtx_avx512.c > > > +++ b/drivers/common/idpf/idpf_common_rxtx_avx512.c > > > @@ -1005,7 +1005,7 @@ idpf_tx_singleq_free_bufs_avx512(struct > > > idpf_tx_queue *txq) > > > struct rte_mbuf *m, *free[txq->rs_thresh]; > > > > > > /* check DD bits on threshold descriptor */ > > > - if ((txq->tx_ring[txq->next_dd].qw1.cmd_dtype & > > > + if ((txq->tx_ring[txq->next_dd].qw1 & > > > rte_cpu_to_le_64(IDPF_TXD_QW1_DTYPE_M)) !=3D > > > > > > rte_cpu_to_le_64(IDPF_TX_DESC_DTYPE_DESC_DONE)) > > > return 0; > > > @@ -1113,15 +1113,14 @@ tx_backlog_entry_avx512(struct > > > idpf_tx_vec_entry *txep, > > > txep[i].mbuf =3D tx_pkts[i]; > > > } > > > > > > -#define IDPF_FLEX_TXD_QW1_BUF_SZ_S 48 static __rte_always_inline > > > void -idpf_singleq_vtx1(volatile struct idpf_flex_tx_desc *txdp, > > > +idpf_singleq_vtx1(volatile struct idpf_base_tx_desc *txdp, > > > struct rte_mbuf *pkt, uint64_t flags) { > > > uint64_t high_qw =3D > > > - (IDPF_TX_DESC_DTYPE_FLEX_DATA << > > > IDPF_FLEX_TXD_QW1_DTYPE_S | > > > - ((uint64_t)flags << IDPF_FLEX_TXD_QW1_CMD_S) | > > > - ((uint64_t)pkt->data_len << > > > IDPF_FLEX_TXD_QW1_BUF_SZ_S)); > > > + (IDPF_TX_DESC_DTYPE_DATA | > > > + ((uint64_t)flags << IDPF_TXD_QW1_CMD_S) | > > > + ((uint64_t)pkt->data_len << IDPF_TXD_QW1_TX_BUF_SZ_S)); > > > > > > __m128i descriptor =3D _mm_set_epi64x(high_qw, > > > pkt->buf_iova + pkt->data_off); > > @@ -1131,11 +1130,11 @@ > > > idpf_singleq_vtx1(volatile struct idpf_flex_tx_desc *txdp, #define > > > IDPF_TX_LEN_MASK 0xAA #define IDPF_TX_OFF_MASK 0x55 static > > > __rte_always_inline void - idpf_singleq_vtx(volatile struct > > > idpf_flex_tx_desc *txdp, > > > +idpf_singleq_vtx(volatile struct idpf_base_tx_desc *txdp, > > > struct rte_mbuf **pkt, uint16_t nb_pkts, uint64_t flags) { > > > - const uint64_t hi_qw_tmpl =3D (IDPF_TX_DESC_DTYPE_FLEX_DATA | > > > - ((uint64_t)flags << IDPF_FLEX_TXD_QW1_CMD_S)); > > > + const uint64_t hi_qw_tmpl =3D (IDPF_TX_DESC_DTYPE_DATA | > > > + ((uint64_t)flags << IDPF_TXD_QW1_CMD_S)); > > > > > > /* if unaligned on 32-bit boundary, do one to align */ > > > if (((uintptr_t)txdp & 0x1F) !=3D 0 && nb_pkts !=3D 0) { @@ -1148,1= 9 > > > +1147,19 @@ idpf_singleq_vtx(volatile struct idpf_flex_tx_desc > > > +*txdp, > > > uint64_t hi_qw3 =3D > > > hi_qw_tmpl | > > > ((uint64_t)pkt[3]->data_len << > > > - IDPF_FLEX_TXD_QW1_BUF_SZ_S); > > > + IDPF_TXD_QW1_TX_BUF_SZ_S); > > > uint64_t hi_qw2 =3D > > > hi_qw_tmpl | > > > ((uint64_t)pkt[2]->data_len << > > > - IDPF_FLEX_TXD_QW1_BUF_SZ_S); > > > + IDPF_TXD_QW1_TX_BUF_SZ_S); > > > uint64_t hi_qw1 =3D > > > hi_qw_tmpl | > > > ((uint64_t)pkt[1]->data_len << > > > - IDPF_FLEX_TXD_QW1_BUF_SZ_S); > > > + IDPF_TXD_QW1_TX_BUF_SZ_S); > > > uint64_t hi_qw0 =3D > > > hi_qw_tmpl | > > > ((uint64_t)pkt[0]->data_len << > > > - IDPF_FLEX_TXD_QW1_BUF_SZ_S); > > > + IDPF_TXD_QW1_TX_BUF_SZ_S); > > > > > > __m512i desc0_3 =3D > > > _mm512_set_epi64 > > > @@ -1187,11 +1186,11 @@ > > idpf_singleq_xmit_fixed_burst_vec_avx512(void > > > *tx_queue, struct rte_mbuf **tx_pk > > > uint16_t nb_pkts) > > > { > > > struct idpf_tx_queue *txq =3D tx_queue; > > > - volatile struct idpf_flex_tx_desc *txdp; > > > + volatile struct idpf_base_tx_desc *txdp; > > > struct idpf_tx_vec_entry *txep; > > > uint16_t n, nb_commit, tx_id; > > > - uint64_t flags =3D IDPF_TX_FLEX_DESC_CMD_EOP; > > > - uint64_t rs =3D IDPF_TX_FLEX_DESC_CMD_RS | flags; > > > + uint64_t flags =3D IDPF_TX_DESC_CMD_EOP; > > > + uint64_t rs =3D IDPF_TX_DESC_CMD_RS | flags; > > > > > > /* cross rx_thresh boundary is not allowed */ > > > nb_pkts =3D RTE_MIN(nb_pkts, txq->rs_thresh); @@ -1238,9 +1237,9 > > @@ > > > idpf_singleq_xmit_fixed_burst_vec_avx512(void *tx_queue, struct > > > rte_mbuf **tx_pk > > > > > > tx_id =3D (uint16_t)(tx_id + nb_commit); > > > if (tx_id > txq->next_rs) { > > > - txq->tx_ring[txq->next_rs].qw1.cmd_dtype |=3D > > > - > > > rte_cpu_to_le_64(((uint64_t)IDPF_TX_FLEX_DESC_CMD_RS) << > > > - IDPF_FLEX_TXD_QW1_CMD_S); > > > + txq->tx_ring[txq->next_rs].qw1 |=3D > > > + > > > rte_cpu_to_le_64(((uint64_t)IDPF_TX_DESC_CMD_RS) << > > > + IDPF_TXD_QW1_CMD_S); > > > txq->next_rs =3D > > > (uint16_t)(txq->next_rs + txq->rs_thresh); > > > } > > > diff --git a/drivers/net/idpf/idpf_rxtx.c > > > b/drivers/net/idpf/idpf_rxtx.c index > > > 3e3d81ca6d..64f2235580 100644 > > > --- a/drivers/net/idpf/idpf_rxtx.c > > > +++ b/drivers/net/idpf/idpf_rxtx.c > > > @@ -74,7 +74,7 @@ idpf_dma_zone_reserve(struct rte_eth_dev *dev, > > > uint16_t queue_idx, > > > ring_size =3D RTE_ALIGN(len * sizeof(struct > > > idpf_flex_tx_sched_desc), > > > IDPF_DMA_MEM_ALIGN); > > > else > > > - ring_size =3D RTE_ALIGN(len * sizeof(struct > > > idpf_flex_tx_desc), > > > + ring_size =3D RTE_ALIGN(len * sizeof(struct > > > idpf_base_tx_desc), > > > IDPF_DMA_MEM_ALIGN); > > > rte_memcpy(ring_name, "idpf Tx ring", sizeof("idpf Tx ring")); > > > break; > > > -- > > > 2.25.1 > > > > Acked-by: Wenjun Wu >=20 > Applied to dpdk-next-net-intel. Reverted due to new change request.