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Ande, Venkat Kumar Subject: [PATCH v1] net/axgbe: read and save the port property register From: Venkat Kumar Ande Read and save the port property registers once during the device probe and = then use the saved values as they are needed. Signed-off-by: Venkat Kumar Ande --- drivers/net/axgbe/axgbe_ethdev.c | 21 +++++---- drivers/net/axgbe/axgbe_ethdev.h | 7 +++ drivers/net/axgbe/axgbe_phy_impl.c | 68 ++++++++++++------------------ 3 files changed, 48 insertions(+), 48 deletions(-) diff --git a/drivers/net/axgbe/axgbe_ethdev.c b/drivers/net/axgbe/axgbe_eth= dev.c index f174d46143..3450374535 100644 --- a/drivers/net/axgbe/axgbe_ethdev.c +++ b/drivers/net/axgbe/axgbe_ethdev.c @@ -2342,23 +2342,28 @@ eth_axgbe_dev_init(struct rte_eth_dev *eth_dev) pdata->arcache =3D AXGBE_DMA_OS_ARCACHE; pdata->awcache =3D AXGBE_DMA_OS_AWCACHE; + /* Read the port property registers */ + pdata->pp0 =3D XP_IOREAD(pdata, XP_PROP_0); + pdata->pp1 =3D XP_IOREAD(pdata, XP_PROP_1); + pdata->pp2 =3D XP_IOREAD(pdata, XP_PROP_2); + pdata->pp3 =3D XP_IOREAD(pdata, XP_PROP_3); + pdata->pp4 =3D XP_IOREAD(pdata, XP_PROP_4); + /* Set the maximum channels and queues */ - reg =3D XP_IOREAD(pdata, XP_PROP_1); - pdata->tx_max_channel_count =3D XP_GET_BITS(reg, XP_PROP_1, MAX_TX_= DMA); - pdata->rx_max_channel_count =3D XP_GET_BITS(reg, XP_PROP_1, MAX_RX_= DMA); - pdata->tx_max_q_count =3D XP_GET_BITS(reg, XP_PROP_1, MAX_TX_QUEUES= ); - pdata->rx_max_q_count =3D XP_GET_BITS(reg, XP_PROP_1, MAX_RX_QUEUES= ); + pdata->tx_max_channel_count =3D XP_GET_BITS(pdata->pp1, XP_PROP_1, = MAX_TX_DMA); + pdata->rx_max_channel_count =3D XP_GET_BITS(pdata->pp1, XP_PROP_1, = MAX_RX_DMA); + pdata->tx_max_q_count =3D XP_GET_BITS(pdata->pp1, XP_PROP_1, MAX_TX= _QUEUES); + pdata->rx_max_q_count =3D XP_GET_BITS(pdata->pp1, XP_PROP_1, +MAX_RX_QUEUES); /* Set the hardware channel and queue counts */ axgbe_set_counts(pdata); /* Set the maximum fifo amounts */ - reg =3D XP_IOREAD(pdata, XP_PROP_2); - pdata->tx_max_fifo_size =3D XP_GET_BITS(reg, XP_PROP_2, TX_FIFO_SIZ= E); + pdata->tx_max_fifo_size =3D XP_GET_BITS(pdata->pp2, XP_PROP_2, +TX_FIFO_SIZE); pdata->tx_max_fifo_size *=3D 16384; pdata->tx_max_fifo_size =3D RTE_MIN(pdata->tx_max_fifo_size, pdata->vdata->tx_max_fifo_size); - pdata->rx_max_fifo_size =3D XP_GET_BITS(reg, XP_PROP_2, RX_FIFO_SIZ= E); + pdata->rx_max_fifo_size =3D XP_GET_BITS(pdata->pp2, XP_PROP_2, +RX_FIFO_SIZE); pdata->rx_max_fifo_size *=3D 16384; pdata->rx_max_fifo_size =3D RTE_MIN(pdata->rx_max_fifo_size, pdata->vdata->rx_max_fifo_size); = diff --git a/drivers/net/axgbe/axgbe_ethdev.h b/drivers/net/axgbe/axgbe_eth= dev.h index 7f19321d88..df5d63c493 100644 --- a/drivers/net/axgbe/axgbe_ethdev.h +++ b/drivers/net/axgbe/axgbe_ethdev.h @@ -539,6 +539,13 @@ struct axgbe_port { void *xprop_regs; /* AXGBE property registers */ void *xi2c_regs; /* AXGBE I2C CSRs */ + /* Port property registers */ + unsigned int pp0; + unsigned int pp1; + unsigned int pp2; + unsigned int pp3; + unsigned int pp4; + bool cdr_track_early; /* XPCS indirect addressing lock */ unsigned int xpcs_window_def_reg; diff --git a/drivers/net/axgbe/axgbe_phy_impl.c b/drivers/net/axgbe/axgbe_p= hy_impl.c index d97fbbfddd..44ff28517c 100644 --- a/drivers/net/axgbe/axgbe_phy_impl.c +++ b/drivers/net/axgbe/axgbe_phy_impl.c @@ -1709,40 +1709,35 @@ static int axgbe_phy_link_status(struct axgbe_port = *pdata, int *an_restart) static void axgbe_phy_sfp_gpio_setup(struct axgbe= _port *pdata) { struct axgbe_phy_data *phy_data =3D pdata->phy_data; - unsigned int reg; - - reg =3D XP_IOREAD(pdata, XP_PROP_3); phy_data->sfp_gpio_address =3D AXGBE_GPIO_ADDRESS_PCA9555 + - XP_GET_BITS(reg, XP_PROP_3, GPIO_ADDR); + XP_GET_BITS(pdata->pp3, XP_PROP_3, GPIO_ADDR); - phy_data->sfp_gpio_mask =3D XP_GET_BITS(reg, XP_PROP_3, GPIO_MASK); + phy_data->sfp_gpio_mask =3D XP_GET_BITS(pdata->pp3, XP_PROP_3, +GPIO_MASK); - phy_data->sfp_gpio_rx_los =3D XP_GET_BITS(reg, XP_PROP_3, + phy_data->sfp_gpio_rx_los =3D XP_GET_BITS(pdata->pp3, XP_PROP_3, GPIO_RX_LOS); - phy_data->sfp_gpio_tx_fault =3D XP_GET_BITS(reg, XP_PROP_3, + phy_data->sfp_gpio_tx_fault =3D XP_GET_BITS(pdata->pp3, XP_PROP_3, GPIO_TX_FAULT); - phy_data->sfp_gpio_mod_absent =3D XP_GET_BITS(reg, XP_PROP_3, + phy_data->sfp_gpio_mod_absent =3D XP_GET_BITS(pdata->pp3, XP_PROP_3= , GPIO_MOD_ABS); - phy_data->sfp_gpio_rate_select =3D XP_GET_BITS(reg, XP_PROP_3, + phy_data->sfp_gpio_rate_select =3D XP_GET_BITS(pdata->pp3, XP_PROP_= 3, GPIO_RATE_SELECT); } static void axgbe_phy_sfp_comm_setup(struct axgbe_port *pdata) { struct axgbe_phy_data *phy_data =3D pdata->phy_data; - unsigned int reg, mux_addr_hi, mux_addr_lo; + unsigned int mux_addr_hi, mux_addr_lo; - reg =3D XP_IOREAD(pdata, XP_PROP_4); - - mux_addr_hi =3D XP_GET_BITS(reg, XP_PROP_4, MUX_ADDR_HI); - mux_addr_lo =3D XP_GET_BITS(reg, XP_PROP_4, MUX_ADDR_LO); + mux_addr_hi =3D XP_GET_BITS(pdata->pp4, XP_PROP_4, MUX_ADDR_HI); + mux_addr_lo =3D XP_GET_BITS(pdata->pp4, XP_PROP_4, MUX_ADDR_LO); if (mux_addr_lo =3D=3D AXGBE_SFP_DIRECT) return; phy_data->sfp_comm =3D AXGBE_SFP_COMM_PCA9545; phy_data->sfp_mux_address =3D (mux_addr_hi << 2) + mux_addr_lo; - phy_data->sfp_mux_channel =3D XP_GET_BITS(reg, XP_PROP_4, MUX_CHAN)= ; + phy_data->sfp_mux_channel =3D XP_GET_BITS(pdata->pp4, XP_PROP_4, +MUX_CHAN); } static void axgbe_phy_sfp_setup(struct axgbe_port *pdata) @@ -1778,12 +177= 3,11 @@ static bool axgbe_phy_redrv_error(struct axgbe_phy_data *phy_data) = static int axgbe_phy_mdio_reset_setup(struct axgbe_port *pdata) { struct axgbe_phy_data *phy_data =3D pdata->phy_data; - unsigned int reg; if (phy_data->conn_type !=3D AXGBE_CONN_TYPE_MDIO) return 0; - reg =3D XP_IOREAD(pdata, XP_PROP_3); - phy_data->mdio_reset =3D XP_GET_BITS(reg, XP_PROP_3, MDIO_RESET); + + phy_data->mdio_reset =3D XP_GET_BITS(pdata->pp3, XP_PROP_3, MDIO_RE= SET); switch (phy_data->mdio_reset) { case AXGBE_MDIO_RESET_NONE: case AXGBE_MDIO_RESET_I2C_GPIO: @@ -1796,12 +1790,12 @@ static int axgbe_phy_mdio_reset_setup(struct axgbe_= port *pdata) } if (phy_data->mdio_reset =3D=3D AXGBE_MDIO_RESET_I2C_GPIO) { phy_data->mdio_reset_addr =3D AXGBE_GPIO_ADDRESS_PCA9555 + - XP_GET_BITS(reg, XP_PROP_3, + XP_GET_BITS(pdata->pp3, XP_PROP_3, MDIO_RESET_I2C_ADDR); - phy_data->mdio_reset_gpio =3D XP_GET_BITS(reg, XP_PROP_3, + phy_data->mdio_reset_gpio =3D XP_GET_BITS(pdata->pp3, XP_PR= OP_3, MDIO_RESET_I2C_GPIO= ); } else if (phy_data->mdio_reset =3D=3D AXGBE_MDIO_RESET_INT_GPIO) { - phy_data->mdio_reset_gpio =3D XP_GET_BITS(reg, XP_PROP_3, + phy_data->mdio_reset_gpio =3D XP_GET_BITS(pdata->pp3, XP_PR= OP_3, MDIO_RESET_INT_GPIO= ); } @@ -1893,12 +1887,9 @@ static bool axgbe_phy_conn_type_mismatch(struct axgb= e_port *pdata) static bool axgbe_phy_port_enabled(struct axgbe_port *pdata) { - unsigned int reg; - - reg =3D XP_IOREAD(pdata, XP_PROP_0); - if (!XP_GET_BITS(reg, XP_PROP_0, PORT_SPEEDS)) + if (!XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_SPEEDS)) return false; - if (!XP_GET_BITS(reg, XP_PROP_0, CONN_TYPE)) + if (!XP_GET_BITS(pdata->pp0, XP_PROP_0, CONN_TYPE)) return false; return true; @@ -2061,7 +2052,6 @@ static int axgbe_phy_reset(struct axgbe_port *pdata) = static int axgbe_phy_init(struct axgbe_port *pdata) { struct axgbe_phy_data *phy_data; - unsigned int reg; int ret; /* Check if enabled */ @@ -2082,19 +2072,17 @@ static int axgbe_phy_init(struct axgbe_port *pdata) } pdata->phy_data =3D phy_data; - reg =3D XP_IOREAD(pdata, XP_PROP_0); - phy_data->port_mode =3D XP_GET_BITS(reg, XP_PROP_0, PORT_MODE); - phy_data->port_id =3D XP_GET_BITS(reg, XP_PROP_0, PORT_ID); - phy_data->port_speeds =3D XP_GET_BITS(reg, XP_PROP_0, PORT_SPEEDS); - phy_data->conn_type =3D XP_GET_BITS(reg, XP_PROP_0, CONN_TYPE); - phy_data->mdio_addr =3D XP_GET_BITS(reg, XP_PROP_0, MDIO_ADDR); - - reg =3D XP_IOREAD(pdata, XP_PROP_4); - phy_data->redrv =3D XP_GET_BITS(reg, XP_PROP_4, REDRV_PRESENT); - phy_data->redrv_if =3D XP_GET_BITS(reg, XP_PROP_4, REDRV_IF); - phy_data->redrv_addr =3D XP_GET_BITS(reg, XP_PROP_4, REDRV_ADDR); - phy_data->redrv_lane =3D XP_GET_BITS(reg, XP_PROP_4, REDRV_LANE); - phy_data->redrv_model =3D XP_GET_BITS(reg, XP_PROP_4, REDRV_MODEL); + phy_data->port_mode =3D XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_MOD= E); + phy_data->port_id =3D XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_ID); + phy_data->port_speeds =3D XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_S= PEEDS); + phy_data->conn_type =3D XP_GET_BITS(pdata->pp0, XP_PROP_0, CONN_TYP= E); + phy_data->mdio_addr =3D XP_GET_BITS(pdata->pp0, XP_PROP_0, MDIO_ADD= R); + + phy_data->redrv =3D XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_PRESEN= T); + phy_data->redrv_if =3D XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_IF)= ; + phy_data->redrv_addr =3D XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_A= DDR); + phy_data->redrv_lane =3D XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_L= ANE); + phy_data->redrv_model =3D XP_GET_BITS(pdata->pp4, XP_PROP_4, +REDRV_MODEL); /* Validate the connection requested */ if (axgbe_phy_conn_type_mismatch(pdata)) { -- 2.34.1