* [dpdk-dev] [PATCH 01/12] net/mlx5: fix software parsing support query
2021-10-06 12:09 [dpdk-dev] [PATCH 00/12] Expand NIC offloads support on Windows Tal Shnaiderman
@ 2021-10-06 12:09 ` Tal Shnaiderman
2021-10-06 12:09 ` [dpdk-dev] [PATCH 02/12] common/mlx5: read software parsing capabilities from DevX Tal Shnaiderman
` (11 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Tal Shnaiderman @ 2021-10-06 12:09 UTC (permalink / raw)
To: dev
Cc: thomas, matan, rasland, asafp, viacheslavo, eilong, kcollins,
idanhac, stable
Currently, the PMD decides if the software parsing
offload can enable outer IPv4 checksum and tunneled
TSO support by checking config->hw_csum and config->tso
respectively.
This is incorrect, the right way is to check the following
flags returned by the mlx5dv_query_device function:
MLX5DV_SW_PARSING - check general swp support.
MLX5DV_SW_PARSING_CSUM - check swp checksum support.
MLX5DV_SW_PARSING_LSO - check swp LSO/TSO support.
The fix enables the offloads according to the correct
flags returned by the kernel.
Fixes: e46821e9fcdc60 ("net/mlx5: separate generic tunnel TSO from the standard one")
Cc: stable@dpdk.org
Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
---
drivers/net/mlx5/linux/mlx5_os.c | 3 ++-
drivers/net/mlx5/linux/mlx5_os.h | 12 ++++++++++++
drivers/net/mlx5/mlx5.h | 2 +-
drivers/net/mlx5/mlx5_txq.c | 15 +++++++++------
4 files changed, 24 insertions(+), 8 deletions(-)
diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c
index 3746057673..a6542629c7 100644
--- a/drivers/net/mlx5/linux/mlx5_os.c
+++ b/drivers/net/mlx5/linux/mlx5_os.c
@@ -1112,7 +1112,8 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,
swp = dv_attr.sw_parsing_caps.sw_parsing_offloads;
DRV_LOG(DEBUG, "SWP support: %u", swp);
#endif
- config->swp = !!swp;
+ config->swp = swp & (MLX5_SW_PARSING_CAP | MLX5_SW_PARSING_CSUM_CAP |
+ MLX5_SW_PARSING_TSO_CAP);
#ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_STRIDING_RQ) {
struct mlx5dv_striding_rq_caps mprq_caps =
diff --git a/drivers/net/mlx5/linux/mlx5_os.h b/drivers/net/mlx5/linux/mlx5_os.h
index 2991d37df2..da036edb72 100644
--- a/drivers/net/mlx5/linux/mlx5_os.h
+++ b/drivers/net/mlx5/linux/mlx5_os.h
@@ -21,4 +21,16 @@ enum {
int mlx5_auxiliary_get_ifindex(const char *sf_name);
+
+enum mlx5_sw_parsing_offloads {
+#ifdef HAVE_IBV_MLX5_MOD_SWP
+ MLX5_SW_PARSING_CAP = MLX5DV_SW_PARSING,
+ MLX5_SW_PARSING_CSUM_CAP = MLX5DV_SW_PARSING_CSUM,
+ MLX5_SW_PARSING_TSO_CAP = MLX5DV_SW_PARSING_LSO,
+#else
+ MLX5_SW_PARSING_CAP = 0,
+ MLX5_SW_PARSING_CSUM_CAP = 0,
+ MLX5_SW_PARSING_TSO_CAP = 0,
+#endif
+};
#endif /* RTE_PMD_MLX5_OS_H_ */
diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h
index 3581414b78..edb4f26d42 100644
--- a/drivers/net/mlx5/mlx5.h
+++ b/drivers/net/mlx5/mlx5.h
@@ -260,7 +260,7 @@ struct mlx5_dev_config {
unsigned int dv_xmeta_en:2; /* Enable extensive flow metadata. */
unsigned int lacp_by_user:1;
/* Enable user to manage LACP traffic. */
- unsigned int swp:1; /* Tx generic tunnel checksum and TSO offload. */
+ unsigned int swp:3; /* Tx generic tunnel checksum and TSO offload. */
unsigned int devx:1; /* Whether devx interface is available or not. */
unsigned int dest_tir:1; /* Whether advanced DR API is available. */
unsigned int reclaim_mode:2; /* Memory reclaim mode. */
diff --git a/drivers/net/mlx5/mlx5_txq.c b/drivers/net/mlx5/mlx5_txq.c
index eb4d34ca55..8dca2b7f79 100644
--- a/drivers/net/mlx5/mlx5_txq.c
+++ b/drivers/net/mlx5/mlx5_txq.c
@@ -111,9 +111,9 @@ mlx5_get_tx_port_offloads(struct rte_eth_dev *dev)
if (config->tx_pp)
offloads |= DEV_TX_OFFLOAD_SEND_ON_TIMESTAMP;
if (config->swp) {
- if (config->hw_csum)
+ if (config->swp & MLX5_SW_PARSING_CSUM_CAP)
offloads |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
- if (config->tso)
+ if (config->swp & MLX5_SW_PARSING_TSO_CAP)
offloads |= (DEV_TX_OFFLOAD_IP_TNL_TSO |
DEV_TX_OFFLOAD_UDP_TNL_TSO);
}
@@ -979,10 +979,13 @@ txq_set_params(struct mlx5_txq_ctrl *txq_ctrl)
txq_ctrl->txq.tso_en = 1;
}
txq_ctrl->txq.tunnel_en = config->tunnel_en | config->swp;
- txq_ctrl->txq.swp_en = ((DEV_TX_OFFLOAD_IP_TNL_TSO |
- DEV_TX_OFFLOAD_UDP_TNL_TSO |
- DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM) &
- txq_ctrl->txq.offloads) && config->swp;
+ txq_ctrl->txq.swp_en = (((DEV_TX_OFFLOAD_IP_TNL_TSO |
+ DEV_TX_OFFLOAD_UDP_TNL_TSO) &
+ txq_ctrl->txq.offloads) && (config->swp &
+ MLX5_SW_PARSING_TSO_CAP)) |
+ ((DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM &
+ txq_ctrl->txq.offloads) && (config->swp &
+ MLX5_SW_PARSING_CSUM_CAP));
}
/**
--
2.16.1.windows.4
^ permalink raw reply [flat|nested] 14+ messages in thread* [dpdk-dev] [PATCH 02/12] common/mlx5: read software parsing capabilities from DevX
2021-10-06 12:09 [dpdk-dev] [PATCH 00/12] Expand NIC offloads support on Windows Tal Shnaiderman
2021-10-06 12:09 ` [dpdk-dev] [PATCH 01/12] net/mlx5: fix software parsing support query Tal Shnaiderman
@ 2021-10-06 12:09 ` Tal Shnaiderman
2021-10-06 12:09 ` [dpdk-dev] [PATCH 03/12] net/mlx5: query software parsing support on Windows Tal Shnaiderman
` (10 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Tal Shnaiderman @ 2021-10-06 12:09 UTC (permalink / raw)
To: dev; +Cc: thomas, matan, rasland, asafp, viacheslavo, eilong, kcollins, idanhac
mlx5 in Windows needs the software parsing hca capabilities
to query the NIC for TSO and Checksum offloading support.
Added the capability as part of the capabilities
queried by the PMD using DevX.
Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
---
drivers/common/mlx5/mlx5_devx_cmds.c | 6 ++++++
drivers/common/mlx5/mlx5_devx_cmds.h | 3 +++
2 files changed, 9 insertions(+)
diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c
index 56407cc332..70ba74e112 100644
--- a/drivers/common/mlx5/mlx5_devx_cmds.c
+++ b/drivers/common/mlx5/mlx5_devx_cmds.c
@@ -991,6 +991,12 @@ mlx5_devx_cmd_query_hca_attr(void *ctx,
hcattr, tunnel_lro_gre);
attr->tunnel_lro_vxlan = MLX5_GET(per_protocol_networking_offload_caps,
hcattr, tunnel_lro_vxlan);
+ attr->swp = MLX5_GET(per_protocol_networking_offload_caps,
+ hcattr, swp);
+ attr->swp_csum = MLX5_GET(per_protocol_networking_offload_caps,
+ hcattr, swp_csum);
+ attr->swp_lso = MLX5_GET(per_protocol_networking_offload_caps,
+ hcattr, swp_lso);
attr->lro_max_msg_sz_mode = MLX5_GET
(per_protocol_networking_offload_caps,
hcattr, lro_max_msg_sz_mode);
diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h
index e576e30f24..caa444bc15 100644
--- a/drivers/common/mlx5/mlx5_devx_cmds.h
+++ b/drivers/common/mlx5/mlx5_devx_cmds.h
@@ -116,6 +116,9 @@ struct mlx5_hca_attr {
uint32_t lro_cap:1;
uint32_t tunnel_lro_gre:1;
uint32_t tunnel_lro_vxlan:1;
+ uint32_t swp:1;
+ uint32_t swp_csum:1;
+ uint32_t swp_lso:1;
uint32_t lro_max_msg_sz_mode:2;
uint32_t lro_timer_supported_periods[MLX5_LRO_NUM_SUPP_PERIODS];
uint16_t lro_min_mss_size;
--
2.16.1.windows.4
^ permalink raw reply [flat|nested] 14+ messages in thread* [dpdk-dev] [PATCH 03/12] net/mlx5: query software parsing support on Windows
2021-10-06 12:09 [dpdk-dev] [PATCH 00/12] Expand NIC offloads support on Windows Tal Shnaiderman
2021-10-06 12:09 ` [dpdk-dev] [PATCH 01/12] net/mlx5: fix software parsing support query Tal Shnaiderman
2021-10-06 12:09 ` [dpdk-dev] [PATCH 02/12] common/mlx5: read software parsing capabilities from DevX Tal Shnaiderman
@ 2021-10-06 12:09 ` Tal Shnaiderman
2021-10-06 12:09 ` [dpdk-dev] [PATCH 04/12] net/mlx5: fix tunneling support query Tal Shnaiderman
` (9 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Tal Shnaiderman @ 2021-10-06 12:09 UTC (permalink / raw)
To: dev; +Cc: thomas, matan, rasland, asafp, viacheslavo, eilong, kcollins, idanhac
Query software parsing supported on the NIC.
Save the offloads values in a config parameter.
This is needed for the outer IPv4 checksum and
IP and UPD tunneled packet TSO support.
Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
---
drivers/net/mlx5/mlx5.c | 16 ++++++++++++++++
drivers/net/mlx5/mlx5.h | 2 ++
drivers/net/mlx5/windows/mlx5_os.c | 6 +++++-
drivers/net/mlx5/windows/mlx5_os.h | 6 ++++++
4 files changed, 29 insertions(+), 1 deletion(-)
diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c
index 45ccfe2784..add07db755 100644
--- a/drivers/net/mlx5/mlx5.c
+++ b/drivers/net/mlx5/mlx5.c
@@ -950,6 +950,22 @@ mlx5_flex_parser_ecpri_release(struct rte_eth_dev *dev)
prf->obj = NULL;
}
+uint32_t
+mlx5_get_supported_sw_parsing_offloads(const struct mlx5_hca_attr *attr)
+{
+ uint32_t sw_parsing_offloads = 0;
+
+ if (attr->swp) {
+ sw_parsing_offloads |= MLX5_SW_PARSING_CAP;
+ if (attr->swp_csum)
+ sw_parsing_offloads |= MLX5_SW_PARSING_CSUM_CAP;
+
+ if (attr->swp_lso)
+ sw_parsing_offloads |= MLX5_SW_PARSING_TSO_CAP;
+ }
+ return sw_parsing_offloads;
+}
+
/*
* Allocate Rx and Tx UARs in robust fashion.
* This routine handles the following UAR allocation issues:
diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h
index edb4f26d42..0694927457 100644
--- a/drivers/net/mlx5/mlx5.h
+++ b/drivers/net/mlx5/mlx5.h
@@ -1828,5 +1828,7 @@ int mlx5_aso_ct_query_by_wqe(struct mlx5_dev_ctx_shared *sh,
struct rte_flow_action_conntrack *profile);
int mlx5_aso_ct_available(struct mlx5_dev_ctx_shared *sh,
struct mlx5_aso_ct_action *ct);
+uint32_t
+mlx5_get_supported_sw_parsing_offloads(const struct mlx5_hca_attr *attr);
#endif /* RTE_PMD_MLX5_H_ */
diff --git a/drivers/net/mlx5/windows/mlx5_os.c b/drivers/net/mlx5/windows/mlx5_os.c
index 26fa927039..1e258e044e 100644
--- a/drivers/net/mlx5/windows/mlx5_os.c
+++ b/drivers/net/mlx5/windows/mlx5_os.c
@@ -169,6 +169,8 @@ mlx5_os_get_dev_attr(void *ctx, struct mlx5_dev_attr *device_attr)
device_attr->max_rwq_indirection_table_size =
1 << hca_attr.rss_ind_tbl_cap;
}
+ device_attr->sw_parsing_offloads =
+ mlx5_get_supported_sw_parsing_offloads(&hca_attr);
pv_iseg = mlx5_glue->query_hca_iseg(mlx5_ctx, &cb_iseg);
if (pv_iseg == NULL) {
DRV_LOG(ERR, "Failed to get device hca_iseg");
@@ -393,7 +395,9 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,
}
DRV_LOG(DEBUG, "MPW isn't supported");
mlx5_os_get_dev_attr(sh->ctx, &device_attr);
- config->swp = 0;
+ config->swp = device_attr.sw_parsing_offloads &
+ (MLX5_SW_PARSING_CAP | MLX5_SW_PARSING_CSUM_CAP |
+ MLX5_SW_PARSING_TSO_CAP);
config->ind_table_max_size =
sh->device_attr.max_rwq_indirection_table_size;
cqe_comp = 0;
diff --git a/drivers/net/mlx5/windows/mlx5_os.h b/drivers/net/mlx5/windows/mlx5_os.h
index 7fe41d4e90..6de683357c 100644
--- a/drivers/net/mlx5/windows/mlx5_os.h
+++ b/drivers/net/mlx5/windows/mlx5_os.h
@@ -16,4 +16,10 @@ enum {
#define MLX5_NAMESIZE MLX5_FS_NAME_MAX
+enum mlx5_sw_parsing_offloads {
+ MLX5_SW_PARSING_CAP = 1 << 0,
+ MLX5_SW_PARSING_CSUM_CAP = 1 << 1,
+ MLX5_SW_PARSING_TSO_CAP = 1 << 2,
+};
+
#endif /* RTE_PMD_MLX5_OS_H_ */
--
2.16.1.windows.4
^ permalink raw reply [flat|nested] 14+ messages in thread* [dpdk-dev] [PATCH 04/12] net/mlx5: fix tunneling support query
2021-10-06 12:09 [dpdk-dev] [PATCH 00/12] Expand NIC offloads support on Windows Tal Shnaiderman
` (2 preceding siblings ...)
2021-10-06 12:09 ` [dpdk-dev] [PATCH 03/12] net/mlx5: query software parsing support on Windows Tal Shnaiderman
@ 2021-10-06 12:09 ` Tal Shnaiderman
2021-10-06 12:09 ` [dpdk-dev] [PATCH 05/12] common/mlx5: read tunneling capabilities from DevX Tal Shnaiderman
` (8 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Tal Shnaiderman @ 2021-10-06 12:09 UTC (permalink / raw)
To: dev
Cc: thomas, matan, rasland, asafp, viacheslavo, eilong, kcollins,
idanhac, stable
Currently, the PMD decides if the tunneling offload
can enable VXLAN/GRE/GENEVE tunneled TSO support by checking
config->tunnel_en (single bit) and config->tso.
This is incorrect, the right way is to check the following
flags returned by the mlx5dv_query_device function:
MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN - if supported the offload
DEV_TX_OFFLOAD_VXLAN_TNL_TSO can be enabled.
MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE - if supported the offload
DEV_TX_OFFLOAD_GRE_TNL_TSO can be enabled.
MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GENEVE - if supported the offload
DEV_TX_OFFLOAD_GENEVE_TNL_TSO can be enabled.
The fix enables the offloads according to the correct
flags returned by the kernel.
Fixes: dbccb4cddcd2f7c ("net/mlx5: convert to new Tx offloads API")
Cc: stable@dpdk.org
Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
---
drivers/net/mlx5/linux/mlx5_os.c | 28 +++++++++++++++++-----------
drivers/net/mlx5/linux/mlx5_os.h | 15 +++++++++++++++
drivers/net/mlx5/mlx5.h | 2 +-
drivers/net/mlx5/mlx5_txq.c | 24 +++++++++++++++++++-----
drivers/net/mlx5/windows/mlx5_os.h | 6 ++++++
5 files changed, 58 insertions(+), 17 deletions(-)
diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c
index a6542629c7..9ac354fabe 100644
--- a/drivers/net/mlx5/linux/mlx5_os.c
+++ b/drivers/net/mlx5/linux/mlx5_os.c
@@ -963,7 +963,6 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,
int err = 0;
unsigned int hw_padding = 0;
unsigned int mps;
- unsigned int tunnel_en = 0;
unsigned int mpls_en = 0;
unsigned int swp = 0;
unsigned int mprq = 0;
@@ -1145,20 +1144,27 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,
config->cqe_comp = 1;
#ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) {
- tunnel_en = ((dv_attr.tunnel_offloads_caps &
- MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN) &&
- (dv_attr.tunnel_offloads_caps &
- MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE) &&
- (dv_attr.tunnel_offloads_caps &
- MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GENEVE));
- }
- DRV_LOG(DEBUG, "tunnel offloading is %ssupported",
- tunnel_en ? "" : "not ");
+ config->tunnel_en = dv_attr.tunnel_offloads_caps &
+ (MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN |
+ MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE |
+ MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GENEVE);
+ }
+ if (config->tunnel_en) {
+ DRV_LOG(DEBUG, "tunnel offloading is supported for %s%s%s",
+ config->tunnel_en &
+ MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN ? "[VXLAN]" : "",
+ config->tunnel_en &
+ MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE ? "[GRE]" : "",
+ config->tunnel_en &
+ MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GENEVE ? "[GENEVE]" : ""
+ );
+ } else {
+ DRV_LOG(DEBUG, "tunnel offloading is not supported");
+ }
#else
DRV_LOG(WARNING,
"tunnel offloading disabled due to old OFED/rdma-core version");
#endif
- config->tunnel_en = tunnel_en;
#ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT
mpls_en = ((dv_attr.tunnel_offloads_caps &
MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_GRE) &&
diff --git a/drivers/net/mlx5/linux/mlx5_os.h b/drivers/net/mlx5/linux/mlx5_os.h
index da036edb72..80c70d713a 100644
--- a/drivers/net/mlx5/linux/mlx5_os.h
+++ b/drivers/net/mlx5/linux/mlx5_os.h
@@ -33,4 +33,19 @@ enum mlx5_sw_parsing_offloads {
MLX5_SW_PARSING_TSO_CAP = 0,
#endif
};
+
+enum mlx5_tunnel_offloads {
+#ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
+ MLX5_TUNNELED_OFFLOADS_VXLAN_CAP =
+ MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN,
+ MLX5_TUNNELED_OFFLOADS_GRE_CAP =
+ MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE,
+ MLX5_TUNNELED_OFFLOADS_GENEVE_CAP =
+ MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GENEVE,
+#else
+ MLX5_TUNNELED_OFFLOADS_VXLAN_CAP = 0,
+ MLX5_TUNNELED_OFFLOADS_GRE_CAP = 0,
+ MLX5_TUNNELED_OFFLOADS_GENEVE_CAP = 0,
+#endif
+};
#endif /* RTE_PMD_MLX5_OS_H_ */
diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h
index 0694927457..58f12cd75c 100644
--- a/drivers/net/mlx5/mlx5.h
+++ b/drivers/net/mlx5/mlx5.h
@@ -244,7 +244,7 @@ struct mlx5_dev_config {
unsigned int hw_padding:1; /* End alignment padding is supported. */
unsigned int vf:1; /* This is a VF. */
unsigned int sf:1; /* This is a SF. */
- unsigned int tunnel_en:1;
+ unsigned int tunnel_en:3;
/* Whether tunnel stateless offloads are supported. */
unsigned int mpls_en:1; /* MPLS over GRE/UDP is enabled. */
unsigned int cqe_comp:1; /* CQE compression is enabled. */
diff --git a/drivers/net/mlx5/mlx5_txq.c b/drivers/net/mlx5/mlx5_txq.c
index 8dca2b7f79..54f42292ac 100644
--- a/drivers/net/mlx5/mlx5_txq.c
+++ b/drivers/net/mlx5/mlx5_txq.c
@@ -120,10 +120,17 @@ mlx5_get_tx_port_offloads(struct rte_eth_dev *dev)
if (config->tunnel_en) {
if (config->hw_csum)
offloads |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
- if (config->tso)
- offloads |= (DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
- DEV_TX_OFFLOAD_GRE_TNL_TSO |
- DEV_TX_OFFLOAD_GENEVE_TNL_TSO);
+ if (config->tso) {
+ if (config->tunnel_en &
+ MLX5_TUNNELED_OFFLOADS_VXLAN_CAP)
+ offloads |= DEV_TX_OFFLOAD_VXLAN_TNL_TSO;
+ if (config->tunnel_en &
+ MLX5_TUNNELED_OFFLOADS_GRE_CAP)
+ offloads |= DEV_TX_OFFLOAD_GRE_TNL_TSO;
+ if (config->tunnel_en &
+ MLX5_TUNNELED_OFFLOADS_GENEVE_CAP)
+ offloads |= DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
+ }
}
if (!config->mprq.enabled)
offloads |= DEV_TX_OFFLOAD_MBUF_FAST_FREE;
@@ -978,7 +985,14 @@ txq_set_params(struct mlx5_txq_ctrl *txq_ctrl)
MLX5_MAX_TSO_HEADER);
txq_ctrl->txq.tso_en = 1;
}
- txq_ctrl->txq.tunnel_en = config->tunnel_en | config->swp;
+ if (((DEV_TX_OFFLOAD_VXLAN_TNL_TSO & txq_ctrl->txq.offloads) &&
+ (config->tunnel_en & MLX5_TUNNELED_OFFLOADS_VXLAN_CAP)) |
+ ((DEV_TX_OFFLOAD_GRE_TNL_TSO & txq_ctrl->txq.offloads) &&
+ (config->tunnel_en & MLX5_TUNNELED_OFFLOADS_GRE_CAP)) |
+ ((DEV_TX_OFFLOAD_GENEVE_TNL_TSO & txq_ctrl->txq.offloads) &&
+ (config->tunnel_en & MLX5_TUNNELED_OFFLOADS_GENEVE_CAP)) |
+ (config->swp & MLX5_SW_PARSING_TSO_CAP))
+ txq_ctrl->txq.tunnel_en = 1;
txq_ctrl->txq.swp_en = (((DEV_TX_OFFLOAD_IP_TNL_TSO |
DEV_TX_OFFLOAD_UDP_TNL_TSO) &
txq_ctrl->txq.offloads) && (config->swp &
diff --git a/drivers/net/mlx5/windows/mlx5_os.h b/drivers/net/mlx5/windows/mlx5_os.h
index 6de683357c..8b58265687 100644
--- a/drivers/net/mlx5/windows/mlx5_os.h
+++ b/drivers/net/mlx5/windows/mlx5_os.h
@@ -22,4 +22,10 @@ enum mlx5_sw_parsing_offloads {
MLX5_SW_PARSING_TSO_CAP = 1 << 2,
};
+enum mlx5_tunnel_offloads {
+ MLX5_TUNNELED_OFFLOADS_VXLAN_CAP = 1 << 0,
+ MLX5_TUNNELED_OFFLOADS_GRE_CAP = 1 << 1,
+ MLX5_TUNNELED_OFFLOADS_GENEVE_CAP = 1 << 2,
+};
+
#endif /* RTE_PMD_MLX5_OS_H_ */
--
2.16.1.windows.4
^ permalink raw reply [flat|nested] 14+ messages in thread* [dpdk-dev] [PATCH 05/12] common/mlx5: read tunneling capabilities from DevX
2021-10-06 12:09 [dpdk-dev] [PATCH 00/12] Expand NIC offloads support on Windows Tal Shnaiderman
` (3 preceding siblings ...)
2021-10-06 12:09 ` [dpdk-dev] [PATCH 04/12] net/mlx5: fix tunneling support query Tal Shnaiderman
@ 2021-10-06 12:09 ` Tal Shnaiderman
2021-10-06 12:09 ` [dpdk-dev] [PATCH 06/12] net/mlx5: query tunneling support on Windows Tal Shnaiderman
` (7 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Tal Shnaiderman @ 2021-10-06 12:09 UTC (permalink / raw)
To: dev; +Cc: thomas, matan, rasland, asafp, viacheslavo, eilong, kcollins, idanhac
mlx5 in Windows needs the tunneling hca capabilities
to query the NIC for Inner TSO offloading support.
Added the capability as part of the capabilities
queried by the PMD using DevX.
Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
---
drivers/common/mlx5/mlx5_devx_cmds.c | 6 ++++++
drivers/common/mlx5/mlx5_devx_cmds.h | 2 ++
2 files changed, 8 insertions(+)
diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c
index 70ba74e112..cd18ab584f 100644
--- a/drivers/common/mlx5/mlx5_devx_cmds.c
+++ b/drivers/common/mlx5/mlx5_devx_cmds.c
@@ -993,6 +993,12 @@ mlx5_devx_cmd_query_hca_attr(void *ctx,
hcattr, tunnel_lro_vxlan);
attr->swp = MLX5_GET(per_protocol_networking_offload_caps,
hcattr, swp);
+ attr->tunnel_stateless_gre =
+ MLX5_GET(per_protocol_networking_offload_caps,
+ hcattr, tunnel_stateless_gre);
+ attr->tunnel_stateless_vxlan =
+ MLX5_GET(per_protocol_networking_offload_caps,
+ hcattr, tunnel_stateless_vxlan);
attr->swp_csum = MLX5_GET(per_protocol_networking_offload_caps,
hcattr, swp_csum);
attr->swp_lso = MLX5_GET(per_protocol_networking_offload_caps,
diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h
index caa444bc15..893a24dd3c 100644
--- a/drivers/common/mlx5/mlx5_devx_cmds.h
+++ b/drivers/common/mlx5/mlx5_devx_cmds.h
@@ -116,6 +116,8 @@ struct mlx5_hca_attr {
uint32_t lro_cap:1;
uint32_t tunnel_lro_gre:1;
uint32_t tunnel_lro_vxlan:1;
+ uint32_t tunnel_stateless_gre:1;
+ uint32_t tunnel_stateless_vxlan:1;
uint32_t swp:1;
uint32_t swp_csum:1;
uint32_t swp_lso:1;
--
2.16.1.windows.4
^ permalink raw reply [flat|nested] 14+ messages in thread* [dpdk-dev] [PATCH 06/12] net/mlx5: query tunneling support on Windows
2021-10-06 12:09 [dpdk-dev] [PATCH 00/12] Expand NIC offloads support on Windows Tal Shnaiderman
` (4 preceding siblings ...)
2021-10-06 12:09 ` [dpdk-dev] [PATCH 05/12] common/mlx5: read tunneling capabilities from DevX Tal Shnaiderman
@ 2021-10-06 12:09 ` Tal Shnaiderman
2021-10-06 12:09 ` [dpdk-dev] [PATCH 07/12] common/mlx5: read TSO capability from DevX Tal Shnaiderman
` (6 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Tal Shnaiderman @ 2021-10-06 12:09 UTC (permalink / raw)
To: dev; +Cc: thomas, matan, rasland, asafp, viacheslavo, eilong, kcollins, idanhac
Query tunneling supported on the NIC.
Save the offloads values in a config parameter.
This is needed for the following TSO support:
DEV_TX_OFFLOAD_VXLAN_TNL_TSO
DEV_TX_OFFLOAD_GRE_TNL_TSO
DEV_TX_OFFLOAD_GENEVE_TNL_TSO
Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
---
drivers/net/mlx5/mlx5.c | 14 ++++++++++++++
drivers/net/mlx5/mlx5.h | 2 ++
drivers/net/mlx5/windows/mlx5_os.c | 20 ++++++++++++++++++--
3 files changed, 34 insertions(+), 2 deletions(-)
diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c
index add07db755..a957bc9938 100644
--- a/drivers/net/mlx5/mlx5.c
+++ b/drivers/net/mlx5/mlx5.c
@@ -966,6 +966,20 @@ mlx5_get_supported_sw_parsing_offloads(const struct mlx5_hca_attr *attr)
return sw_parsing_offloads;
}
+uint32_t
+mlx5_get_supported_tunneling_offloads(const struct mlx5_hca_attr *attr)
+{
+ uint32_t tn_offloads = 0;
+
+ if (attr->tunnel_stateless_vxlan)
+ tn_offloads |= MLX5_TUNNELED_OFFLOADS_VXLAN_CAP;
+ if (attr->tunnel_stateless_gre)
+ tn_offloads |= MLX5_TUNNELED_OFFLOADS_GRE_CAP;
+ if (attr->tunnel_stateless_geneve_rx)
+ tn_offloads |= MLX5_TUNNELED_OFFLOADS_GENEVE_CAP;
+ return tn_offloads;
+}
+
/*
* Allocate Rx and Tx UARs in robust fashion.
* This routine handles the following UAR allocation issues:
diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h
index 58f12cd75c..0dbb9aacb8 100644
--- a/drivers/net/mlx5/mlx5.h
+++ b/drivers/net/mlx5/mlx5.h
@@ -1830,5 +1830,7 @@ int mlx5_aso_ct_available(struct mlx5_dev_ctx_shared *sh,
struct mlx5_aso_ct_action *ct);
uint32_t
mlx5_get_supported_sw_parsing_offloads(const struct mlx5_hca_attr *attr);
+uint32_t
+mlx5_get_supported_tunneling_offloads(const struct mlx5_hca_attr *attr);
#endif /* RTE_PMD_MLX5_H_ */
diff --git a/drivers/net/mlx5/windows/mlx5_os.c b/drivers/net/mlx5/windows/mlx5_os.c
index 1e258e044e..fab7d7efcb 100644
--- a/drivers/net/mlx5/windows/mlx5_os.c
+++ b/drivers/net/mlx5/windows/mlx5_os.c
@@ -171,6 +171,8 @@ mlx5_os_get_dev_attr(void *ctx, struct mlx5_dev_attr *device_attr)
}
device_attr->sw_parsing_offloads =
mlx5_get_supported_sw_parsing_offloads(&hca_attr);
+ device_attr->tunnel_offloads_caps =
+ mlx5_get_supported_tunneling_offloads(&hca_attr);
pv_iseg = mlx5_glue->query_hca_iseg(mlx5_ctx, &cb_iseg);
if (pv_iseg == NULL) {
DRV_LOG(ERR, "Failed to get device hca_iseg");
@@ -402,8 +404,22 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,
sh->device_attr.max_rwq_indirection_table_size;
cqe_comp = 0;
config->cqe_comp = cqe_comp;
- DRV_LOG(DEBUG, "tunnel offloading is not supported");
- config->tunnel_en = 0;
+ config->tunnel_en = device_attr.tunnel_offloads_caps &
+ (MLX5_TUNNELED_OFFLOADS_VXLAN_CAP |
+ MLX5_TUNNELED_OFFLOADS_GRE_CAP |
+ MLX5_TUNNELED_OFFLOADS_GENEVE_CAP);
+ if (config->tunnel_en) {
+ DRV_LOG(DEBUG, "tunnel offloading is supported for %s%s%s",
+ config->tunnel_en &
+ MLX5_TUNNELED_OFFLOADS_VXLAN_CAP ? "[VXLAN]" : "",
+ config->tunnel_en &
+ MLX5_TUNNELED_OFFLOADS_GRE_CAP ? "[GRE]" : "",
+ config->tunnel_en &
+ MLX5_TUNNELED_OFFLOADS_GENEVE_CAP ? "[GENEVE]" : ""
+ );
+ } else {
+ DRV_LOG(DEBUG, "tunnel offloading is not supported");
+ }
DRV_LOG(DEBUG, "MPLS over GRE/UDP tunnel offloading is no supported");
config->mpls_en = 0;
/* Allocate private eth device data. */
--
2.16.1.windows.4
^ permalink raw reply [flat|nested] 14+ messages in thread* [dpdk-dev] [PATCH 07/12] common/mlx5: read TSO capability from DevX
2021-10-06 12:09 [dpdk-dev] [PATCH 00/12] Expand NIC offloads support on Windows Tal Shnaiderman
` (5 preceding siblings ...)
2021-10-06 12:09 ` [dpdk-dev] [PATCH 06/12] net/mlx5: query tunneling support on Windows Tal Shnaiderman
@ 2021-10-06 12:09 ` Tal Shnaiderman
2021-10-06 12:09 ` [dpdk-dev] [PATCH 08/12] net/mlx5: support TSO offload on Windows Tal Shnaiderman
` (5 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Tal Shnaiderman @ 2021-10-06 12:09 UTC (permalink / raw)
To: dev; +Cc: thomas, matan, rasland, asafp, viacheslavo, eilong, kcollins, idanhac
mlx5 in Windows needs the hca capability max_lso_cap
to query the NIC for TSO offloading support.
Added the capability as part of the capabilities
queried by the PMD using DevX.
Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
---
drivers/common/mlx5/mlx5_devx_cmds.c | 2 ++
drivers/common/mlx5/mlx5_devx_cmds.h | 1 +
2 files changed, 3 insertions(+)
diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c
index cd18ab584f..be3c3e61d1 100644
--- a/drivers/common/mlx5/mlx5_devx_cmds.c
+++ b/drivers/common/mlx5/mlx5_devx_cmds.c
@@ -987,6 +987,8 @@ mlx5_devx_cmd_query_hca_attr(void *ctx,
hcattr, csum_cap);
attr->lro_cap = MLX5_GET(per_protocol_networking_offload_caps, hcattr,
lro_cap);
+ attr->max_lso_cap = MLX5_GET(per_protocol_networking_offload_caps,
+ hcattr, max_lso_cap);
attr->tunnel_lro_gre = MLX5_GET(per_protocol_networking_offload_caps,
hcattr, tunnel_lro_gre);
attr->tunnel_lro_vxlan = MLX5_GET(per_protocol_networking_offload_caps,
diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h
index 893a24dd3c..7a0155558e 100644
--- a/drivers/common/mlx5/mlx5_devx_cmds.h
+++ b/drivers/common/mlx5/mlx5_devx_cmds.h
@@ -113,6 +113,7 @@ struct mlx5_hca_attr {
uint32_t tunnel_stateless_geneve_rx:1;
uint32_t geneve_max_opt_len:1; /* 0x0: 14DW, 0x1: 63DW */
uint32_t tunnel_stateless_gtp:1;
+ uint32_t max_lso_cap;
uint32_t lro_cap:1;
uint32_t tunnel_lro_gre:1;
uint32_t tunnel_lro_vxlan:1;
--
2.16.1.windows.4
^ permalink raw reply [flat|nested] 14+ messages in thread* [dpdk-dev] [PATCH 08/12] net/mlx5: support TSO offload on Windows
2021-10-06 12:09 [dpdk-dev] [PATCH 00/12] Expand NIC offloads support on Windows Tal Shnaiderman
` (6 preceding siblings ...)
2021-10-06 12:09 ` [dpdk-dev] [PATCH 07/12] common/mlx5: read TSO capability from DevX Tal Shnaiderman
@ 2021-10-06 12:09 ` Tal Shnaiderman
2021-10-06 12:09 ` [dpdk-dev] [PATCH 09/12] common/mlx5: read VLAN capability from DevX Tal Shnaiderman
` (4 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Tal Shnaiderman @ 2021-10-06 12:09 UTC (permalink / raw)
To: dev; +Cc: thomas, matan, rasland, asafp, viacheslavo, eilong, kcollins, idanhac
Support of the TSO offloading by checking
the relevant FW capability for NIC support.
Supported offloads:
DEV_TX_OFFLOAD_TCP_TSO
DEV_TX_OFFLOAD_VXLAN_TNL_TSO
DEV_TX_OFFLOAD_GRE_TNL_TSO
DEV_TX_OFFLOAD_GENEVE_TNL_TSO
Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
---
drivers/net/mlx5/windows/mlx5_os.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/net/mlx5/windows/mlx5_os.c b/drivers/net/mlx5/windows/mlx5_os.c
index fab7d7efcb..194cb7d9ad 100644
--- a/drivers/net/mlx5/windows/mlx5_os.c
+++ b/drivers/net/mlx5/windows/mlx5_os.c
@@ -165,6 +165,7 @@ mlx5_os_get_dev_attr(void *ctx, struct mlx5_dev_attr *device_attr)
device_attr->max_pd = 1 << hca_attr.log_max_pd;
device_attr->max_srq = 1 << hca_attr.log_max_srq;
device_attr->max_srq_wr = 1 << hca_attr.log_max_srq_sz;
+ device_attr->max_tso = 1 << hca_attr.max_lso_cap;
if (hca_attr.rss_ind_tbl_cap) {
device_attr->max_rwq_indirection_table_size =
1 << hca_attr.rss_ind_tbl_cap;
@@ -494,6 +495,7 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,
DRV_LOG(DEBUG, "Rx end alignment padding isn't supported");
config->hw_padding = 0;
}
+ config->tso = (sh->device_attr.max_tso > 0);
if (config->tso)
config->tso_max_payload_sz = sh->device_attr.max_tso;
DRV_LOG(DEBUG, "%sMPS is %s.",
--
2.16.1.windows.4
^ permalink raw reply [flat|nested] 14+ messages in thread* [dpdk-dev] [PATCH 09/12] common/mlx5: read VLAN capability from DevX
2021-10-06 12:09 [dpdk-dev] [PATCH 00/12] Expand NIC offloads support on Windows Tal Shnaiderman
` (7 preceding siblings ...)
2021-10-06 12:09 ` [dpdk-dev] [PATCH 08/12] net/mlx5: support TSO offload on Windows Tal Shnaiderman
@ 2021-10-06 12:09 ` Tal Shnaiderman
2021-10-06 12:09 ` [dpdk-dev] [PATCH 10/12] net/mlx5: support VLAN stripping offload on Windows Tal Shnaiderman
` (3 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Tal Shnaiderman @ 2021-10-06 12:09 UTC (permalink / raw)
To: dev; +Cc: thomas, matan, rasland, asafp, viacheslavo, eilong, kcollins, idanhac
mlx5 in Windows needs the hca capability vlan_cap
to query the NIC for VLAN stripping support
Added the capability as part of the capabilities
queried by the PMD using DevX.
Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
---
drivers/common/mlx5/mlx5_devx_cmds.c | 2 ++
drivers/common/mlx5/mlx5_devx_cmds.h | 1 +
2 files changed, 3 insertions(+)
diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c
index be3c3e61d1..deee4954f4 100644
--- a/drivers/common/mlx5/mlx5_devx_cmds.c
+++ b/drivers/common/mlx5/mlx5_devx_cmds.c
@@ -985,6 +985,8 @@ mlx5_devx_cmd_query_hca_attr(void *ctx,
hcattr, wqe_vlan_insert);
attr->csum_cap = MLX5_GET(per_protocol_networking_offload_caps,
hcattr, csum_cap);
+ attr->vlan_cap = MLX5_GET(per_protocol_networking_offload_caps,
+ hcattr, vlan_cap);
attr->lro_cap = MLX5_GET(per_protocol_networking_offload_caps, hcattr,
lro_cap);
attr->max_lso_cap = MLX5_GET(per_protocol_networking_offload_caps,
diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h
index 7a0155558e..f4aa851cd0 100644
--- a/drivers/common/mlx5/mlx5_devx_cmds.h
+++ b/drivers/common/mlx5/mlx5_devx_cmds.h
@@ -108,6 +108,7 @@ struct mlx5_hca_attr {
uint32_t eth_virt:1;
uint32_t wqe_vlan_insert:1;
uint32_t csum_cap:1;
+ uint32_t vlan_cap:1;
uint32_t wqe_inline_mode:2;
uint32_t vport_inline_mode:3;
uint32_t tunnel_stateless_geneve_rx:1;
--
2.16.1.windows.4
^ permalink raw reply [flat|nested] 14+ messages in thread* [dpdk-dev] [PATCH 10/12] net/mlx5: support VLAN stripping offload on Windows
2021-10-06 12:09 [dpdk-dev] [PATCH 00/12] Expand NIC offloads support on Windows Tal Shnaiderman
` (8 preceding siblings ...)
2021-10-06 12:09 ` [dpdk-dev] [PATCH 09/12] common/mlx5: read VLAN capability from DevX Tal Shnaiderman
@ 2021-10-06 12:09 ` Tal Shnaiderman
2021-10-06 12:09 ` [dpdk-dev] [PATCH 11/12] common/mlx5: read FCS scattering capability from DevX Tal Shnaiderman
` (2 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Tal Shnaiderman @ 2021-10-06 12:09 UTC (permalink / raw)
To: dev; +Cc: thomas, matan, rasland, asafp, viacheslavo, eilong, kcollins, idanhac
Support of the VLAN stripping offloading by checking
the relevant FW capability (vlan_cap) for NIC support.
Supported offload:
DEV_RX_OFFLOAD_VLAN_STRIP
Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
---
drivers/net/mlx5/windows/mlx5_flow_os.h | 1 +
drivers/net/mlx5/windows/mlx5_os.c | 5 +++--
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/net/mlx5/windows/mlx5_flow_os.h b/drivers/net/mlx5/windows/mlx5_flow_os.h
index df92f25ce6..dfcb012334 100644
--- a/drivers/net/mlx5/windows/mlx5_flow_os.h
+++ b/drivers/net/mlx5/windows/mlx5_flow_os.h
@@ -44,6 +44,7 @@ mlx5_flow_os_item_supported(int item)
case RTE_FLOW_ITEM_TYPE_UDP:
case RTE_FLOW_ITEM_TYPE_TCP:
case RTE_FLOW_ITEM_TYPE_IPV6:
+ case RTE_FLOW_ITEM_TYPE_VLAN:
return true;
default:
return false;
diff --git a/drivers/net/mlx5/windows/mlx5_os.c b/drivers/net/mlx5/windows/mlx5_os.c
index 194cb7d9ad..5b941cdb19 100644
--- a/drivers/net/mlx5/windows/mlx5_os.c
+++ b/drivers/net/mlx5/windows/mlx5_os.c
@@ -489,8 +489,6 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,
config->ind_table_max_size = ETH_RSS_RETA_SIZE_512;
DRV_LOG(DEBUG, "maximum Rx indirection table size is %u",
config->ind_table_max_size);
- DRV_LOG(DEBUG, "VLAN stripping is %ssupported",
- (config->hw_vlan_strip ? "" : "not "));
if (config->hw_padding) {
DRV_LOG(DEBUG, "Rx end alignment padding isn't supported");
config->hw_padding = 0;
@@ -524,6 +522,9 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,
config->hw_csum = config->hca_attr.csum_cap;
DRV_LOG(DEBUG, "checksum offloading is %ssupported",
(config->hw_csum ? "" : "not "));
+ config->hw_vlan_strip = config->hca_attr.vlan_cap;
+ DRV_LOG(DEBUG, "VLAN stripping is %ssupported",
+ (config->hw_vlan_strip ? "" : "not "));
}
if (config->devx) {
uint32_t reg[MLX5_ST_SZ_DW(register_mtutc)];
--
2.16.1.windows.4
^ permalink raw reply [flat|nested] 14+ messages in thread* [dpdk-dev] [PATCH 11/12] common/mlx5: read FCS scattering capability from DevX
2021-10-06 12:09 [dpdk-dev] [PATCH 00/12] Expand NIC offloads support on Windows Tal Shnaiderman
` (9 preceding siblings ...)
2021-10-06 12:09 ` [dpdk-dev] [PATCH 10/12] net/mlx5: support VLAN stripping offload on Windows Tal Shnaiderman
@ 2021-10-06 12:09 ` Tal Shnaiderman
2021-10-06 12:09 ` [dpdk-dev] [PATCH 12/12] net/mlx5: support keep-CRC offload on Windows Tal Shnaiderman
2021-10-06 19:18 ` [dpdk-dev] [PATCH 00/12] Expand NIC offloads support " Idan Hackmon
12 siblings, 0 replies; 14+ messages in thread
From: Tal Shnaiderman @ 2021-10-06 12:09 UTC (permalink / raw)
To: dev; +Cc: thomas, matan, rasland, asafp, viacheslavo, eilong, kcollins, idanhac
mlx5 in Windows needs the hca capability scatter_fcs
to query the NIC support for the CRC keeping offload.
Added the capability as part of the capabilities
queried by the PMD using DevX.
Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
---
drivers/common/mlx5/mlx5_devx_cmds.c | 2 ++
drivers/common/mlx5/mlx5_devx_cmds.h | 1 +
2 files changed, 3 insertions(+)
diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c
index deee4954f4..33c064a418 100644
--- a/drivers/common/mlx5/mlx5_devx_cmds.c
+++ b/drivers/common/mlx5/mlx5_devx_cmds.c
@@ -991,6 +991,8 @@ mlx5_devx_cmd_query_hca_attr(void *ctx,
lro_cap);
attr->max_lso_cap = MLX5_GET(per_protocol_networking_offload_caps,
hcattr, max_lso_cap);
+ attr->scatter_fcs = MLX5_GET(per_protocol_networking_offload_caps,
+ hcattr, scatter_fcs);
attr->tunnel_lro_gre = MLX5_GET(per_protocol_networking_offload_caps,
hcattr, tunnel_lro_gre);
attr->tunnel_lro_vxlan = MLX5_GET(per_protocol_networking_offload_caps,
diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h
index f4aa851cd0..6b9f191a69 100644
--- a/drivers/common/mlx5/mlx5_devx_cmds.h
+++ b/drivers/common/mlx5/mlx5_devx_cmds.h
@@ -115,6 +115,7 @@ struct mlx5_hca_attr {
uint32_t geneve_max_opt_len:1; /* 0x0: 14DW, 0x1: 63DW */
uint32_t tunnel_stateless_gtp:1;
uint32_t max_lso_cap;
+ uint32_t scatter_fcs:1;
uint32_t lro_cap:1;
uint32_t tunnel_lro_gre:1;
uint32_t tunnel_lro_vxlan:1;
--
2.16.1.windows.4
^ permalink raw reply [flat|nested] 14+ messages in thread* [dpdk-dev] [PATCH 12/12] net/mlx5: support keep-CRC offload on Windows
2021-10-06 12:09 [dpdk-dev] [PATCH 00/12] Expand NIC offloads support on Windows Tal Shnaiderman
` (10 preceding siblings ...)
2021-10-06 12:09 ` [dpdk-dev] [PATCH 11/12] common/mlx5: read FCS scattering capability from DevX Tal Shnaiderman
@ 2021-10-06 12:09 ` Tal Shnaiderman
2021-10-06 19:18 ` [dpdk-dev] [PATCH 00/12] Expand NIC offloads support " Idan Hackmon
12 siblings, 0 replies; 14+ messages in thread
From: Tal Shnaiderman @ 2021-10-06 12:09 UTC (permalink / raw)
To: dev; +Cc: thomas, matan, rasland, asafp, viacheslavo, eilong, kcollins, idanhac
Support of the keep-CRC offloading by checking
the relevant FW capability (scatter_fcs) for NIC support.
Supported offload:
DEV_RX_OFFLOAD_KEEP_CRC
Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
---
drivers/net/mlx5/windows/mlx5_os.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/net/mlx5/windows/mlx5_os.c b/drivers/net/mlx5/windows/mlx5_os.c
index 5b941cdb19..896b6896b7 100644
--- a/drivers/net/mlx5/windows/mlx5_os.c
+++ b/drivers/net/mlx5/windows/mlx5_os.c
@@ -525,6 +525,7 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,
config->hw_vlan_strip = config->hca_attr.vlan_cap;
DRV_LOG(DEBUG, "VLAN stripping is %ssupported",
(config->hw_vlan_strip ? "" : "not "));
+ config->hw_fcs_strip = config->hca_attr.scatter_fcs;
}
if (config->devx) {
uint32_t reg[MLX5_ST_SZ_DW(register_mtutc)];
--
2.16.1.windows.4
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [dpdk-dev] [PATCH 00/12] Expand NIC offloads support on Windows
2021-10-06 12:09 [dpdk-dev] [PATCH 00/12] Expand NIC offloads support on Windows Tal Shnaiderman
` (11 preceding siblings ...)
2021-10-06 12:09 ` [dpdk-dev] [PATCH 12/12] net/mlx5: support keep-CRC offload on Windows Tal Shnaiderman
@ 2021-10-06 19:18 ` Idan Hackmon
12 siblings, 0 replies; 14+ messages in thread
From: Idan Hackmon @ 2021-10-06 19:18 UTC (permalink / raw)
To: Tal Shnaiderman, dev
Cc: NBU-Contact-Thomas Monjalon, Matan Azrad, Raslan Darawsheh,
Asaf Penso, Slava Ovsiienko, Eilon Greenstein, Kyle Collins
> Subject: [PATCH 00/12] Expand NIC offloads support on Windows
>
> The series supports a group of NIC offloads on Windows:
>
> DEV_TX_OFFLOAD_TCP_TSO
> DEV_TX_OFFLOAD_VXLAN_TNL_TSO
> DEV_TX_OFFLOAD_GRE_TNL_TSO
> DEV_TX_OFFLOAD_GENEVE_TNL_TSO
> DEV_RX_OFFLOAD_VLAN_STRIP
> DEV_RX_OFFLOAD_KEEP_CRC
>
> Tal Shnaiderman (12):
> net/mlx5: fix software parsing support query
> common/mlx5: read software parsing capabilities from DevX
> net/mlx5: query software parsing support on Windows
> net/mlx5: fix tunneling support query
> common/mlx5: read tunneling capabilities from DevX
> net/mlx5: query tunneling support on Windows
> common/mlx5: read TSO capability from DevX
> net/mlx5: support TSO offload on Windows
> common/mlx5: read VLAN capability from DevX
> net/mlx5: support VLAN stripping offload on Windows
> common/mlx5: read FCS scattering capability from DevX
> net/mlx5: support keep-CRC offload on Windows
>
> drivers/common/mlx5/mlx5_devx_cmds.c | 18 +++++++++++++++
> drivers/common/mlx5/mlx5_devx_cmds.h | 8 +++++++
> drivers/net/mlx5/linux/mlx5_os.c | 31 ++++++++++++++++----------
> drivers/net/mlx5/linux/mlx5_os.h | 27 +++++++++++++++++++++++
> drivers/net/mlx5/mlx5.c | 30 +++++++++++++++++++++++++
> drivers/net/mlx5/mlx5.h | 8 +++++--
> drivers/net/mlx5/mlx5_txq.c | 39 +++++++++++++++++++++++--------
> --
> drivers/net/mlx5/windows/mlx5_flow_os.h | 1 +
> drivers/net/mlx5/windows/mlx5_os.c | 34 +++++++++++++++++++++++-
> ----
> drivers/net/mlx5/windows/mlx5_os.h | 12 ++++++++++
> 10 files changed, 178 insertions(+), 30 deletions(-)
>
> --
> 2.16.1.windows.4
Tested-by: Idan Hackmon <idanhac@nvidia.com>
^ permalink raw reply [flat|nested] 14+ messages in thread