From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 535BFA0544; Tue, 7 Jun 2022 04:42:48 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1B6CC406B4; Tue, 7 Jun 2022 04:42:48 +0200 (CEST) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mails.dpdk.org (Postfix) with ESMTP id A3CED40156; Tue, 7 Jun 2022 04:42:45 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1654569766; x=1686105766; h=from:to:cc:subject:date:message-id:references: in-reply-to:content-transfer-encoding:mime-version; bh=HMlm1bsf/U5CyYIzuXZoel0PQfqddIy0BbnxmldXAdA=; b=XypCH+hz9XzC/LlPmWSwbEjgoXuAnsbQ/M0raGAf0pUVMw4ix+LmL8/C qFka3P0OAFtGk3b3k4Pr4yOFs1GMOVUe+iCQ+UgtXGYuw801VcgkdBW2p moOB4YrF32jIt4mNfiQhyxWDSz0AfgzUsZcjCBtQPqEBIdvBL5D84Z+Ie UY4W1O8hDFhhgeDd88PS7ypCNF1cjw32wT6RXsphNczUNoH+auQE0B3bW xsZFdOj59jfbdC9rFfosV/JunfCslIoyRaERb3wdJ2jqXztIjZq56lQjH PLpd3aLXcocZOKdhBds4kc6XMAhTnyxlTXyqgUbQ9qfqqQAKeOVwSEarm Q==; X-IronPort-AV: E=McAfee;i="6400,9594,10370"; a="274240513" X-IronPort-AV: E=Sophos;i="5.91,282,1647327600"; d="scan'208";a="274240513" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Jun 2022 19:42:44 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.91,282,1647327600"; d="scan'208";a="532422140" Received: from fmsmsx605.amr.corp.intel.com ([10.18.126.85]) by orsmga003.jf.intel.com with ESMTP; 06 Jun 2022 19:42:44 -0700 Received: from fmsmsx610.amr.corp.intel.com (10.18.126.90) by fmsmsx605.amr.corp.intel.com (10.18.126.85) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.27; Mon, 6 Jun 2022 19:42:43 -0700 Received: from fmsedg602.ED.cps.intel.com (10.1.192.136) by fmsmsx610.amr.corp.intel.com (10.18.126.90) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.27 via Frontend Transport; Mon, 6 Jun 2022 19:42:43 -0700 Received: from NAM02-BN1-obe.outbound.protection.outlook.com (104.47.51.46) by edgegateway.intel.com (192.55.55.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2308.27; Mon, 6 Jun 2022 19:42:43 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Qgsz0v7eU4A3cePsvyvguAeMXBG/cn92+5uUQgxn8req4fMIOHaDbt3ZXqa0NBQBsW16j+MvaD9GcR8+7SAasCMH+30drxYwhOoJRBj2D9O3wHznFs1j1K7N6kKkdqTGzn+Y8JfdKkzYbAWL//dR17+IyuOu/nfXzIZLN0NBproLvA5R8S0kyzbjWirMBfyFNJepDFVG5fOkK3AWX8BSPyYY8NiMYw2LZMe41E4TP3ycTeDP8DGoJ3tnoMpnkrV2HlWcBBKrb5u8NJxHntb0gJtKgZVe1Q5Y+ugAC51IQfgyBhujLd5A6u246sr3Q75zIE64/TaXVyLD0lA9k7R2Lw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=ZCFfecHgYhbrVTr3t1GgNjeTy0FE574U7BWBmWalrBI=; b=BM0SHyqDLIrHaOS5GLuIr7WgiJm4Ypv6L2s2lEb/WjOQmkvMypw664Emn2hH87An06LYgNLolNSdqt+0FTUoFHCO68nsjRA+kZjExSbZQs1FiYyRBsDKQzzZwLg6dvxJ7I+rT6qY1srsu1yhNBshwHve5WAePu+djzG1nLXzYI00G22yY25YQo90UbTPivHef7/u6d4fHR+r/4TB9PJeugnswJE4AwAIXwZHPxLk3D5b2IpqQnynZhXdncVFJuWPGSl+7Zmnwtpk4y4abwnQKVQcanF8Kx4nOKxkdYMt3koYmuiTrkI/xMbKpwBJpaP0S87/eyC8uBwp/so8p4aDfA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none Received: from DM6PR11MB3530.namprd11.prod.outlook.com (2603:10b6:5:72::19) by DM4PR11MB5970.namprd11.prod.outlook.com (2603:10b6:8:5d::6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5293.19; Tue, 7 Jun 2022 02:42:41 +0000 Received: from DM6PR11MB3530.namprd11.prod.outlook.com ([fe80::3d0e:6e37:569:cd07]) by DM6PR11MB3530.namprd11.prod.outlook.com ([fe80::3d0e:6e37:569:cd07%6]) with mapi id 15.20.5314.019; Tue, 7 Jun 2022 02:42:41 +0000 From: "Huang, Wei" To: "Zhang, Tianfei" , "dev@dpdk.org" , "thomas@monjalon.net" , "nipun.gupta@nxp.com" , "hemant.agrawal@nxp.com" CC: "stable@dpdk.org" , "Xu, Rosen" , "Zhang, Qi Z" Subject: RE: [PATCH v5 3/5] raw/afu_mf: add HE-LBK AFU driver Thread-Topic: [PATCH v5 3/5] raw/afu_mf: add HE-LBK AFU driver Thread-Index: AQHYcYrdKwwfxqtw506aHpwevmPVoa1BqeEAgAGjHKA= Date: Tue, 7 Jun 2022 02:42:41 +0000 Message-ID: References: <1652939560-15786-1-git-send-email-wei.huang@intel.com> <1653629824-4535-1-git-send-email-wei.huang@intel.com> <1653629824-4535-4-git-send-email-wei.huang@intel.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-reaction: no-action dlp-version: 11.6.500.17 authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: c94db666-8722-4c29-f92f-08da482f649c x-ms-traffictypediagnostic: DM4PR11MB5970:EE_ x-microsoft-antispam-prvs: x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: zEfOyzObXfvSdg7BIdARYnVos6dXXB/WoO/F4rDgGq55L3erOoEur0CnzG3FB8uWQEZop469hXbb1M6BOXOwyF7/hYxfdl8Eo/cS1+DsQxgtmRxpqUqYTEfO21zHC+B+7oZLW2R6o308jVopKMZU6+1QqyLALVY3DCeBwXawTHDOzSzZiS8nHBnyaUrIHKE2LowQwhWiJW4PZObCoiBu8iMLtHVIl9tfZt9eX5aWe2Lww1g66zb8r7r9TVsV4C+e2BtxqbsfC6asdkz9BzAFtaHJL3S+r4H2oHCLZtJ7VniOs5eM/M9kJOoqX0J3kcnW3Gvt/9zxzuacsRxDawd3/g20K1HhSAgfASZ6oN/LqoV6fajVWqno/6XNEqhkXwW3HakTZwlggO8AHr57LDvj1A3z7l/ilAUzXwb0H+J5YzGjFAbUwGmzzbeRGClOkxQ8fLH/Ba5jPNkF6m6U2eCFyhKS36FXtl+uw8U5XjshPaqKk+zhLaKES0VviV4S8wGW1NKkSyKLnA4/ImJgaAZc+uaXUdZf8p90qaYbczqyosVT8lGsIlrzEZoVFgaTwDnERjI7jdRF/F5p/EJLDwxJ5t6N6cal+Eri70Fl51OPQrk2yt35VNECOzRmygIpSc0ZtO/cnDzfMzhxGrX+OkO3VcJNq62wl6hnGClTXNeCdENQi/jWxEjWU92DwsUpXmUEjnOn0Bcjlxt5medO+fF3Yg== x-forefront-antispam-report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:DM6PR11MB3530.namprd11.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230001)(366004)(83380400001)(38070700005)(55016003)(66446008)(66476007)(508600001)(8676002)(64756008)(5660300002)(33656002)(71200400001)(76116006)(66556008)(186003)(66946007)(4326008)(107886003)(52536014)(316002)(9686003)(122000001)(38100700002)(82960400001)(26005)(86362001)(53546011)(30864003)(8936002)(6506007)(7696005)(54906003)(2906002)(110136005)(579004); DIR:OUT; SFP:1102; x-ms-exchange-antispam-messagedata-chunkcount: 1 x-ms-exchange-antispam-messagedata-0: =?us-ascii?Q?fDRGds36jhIgdOowUWHfJ+7V/0NWjCOxRgi/hqN/VuzR4rKnag3cthfMICTN?= =?us-ascii?Q?GEU3hNBSRv45T8nhr0TYLl7jeNxNhipyLweJhO0GNPi2WpqXFxZ97DxRwxIZ?= =?us-ascii?Q?2iiS50p6LpU/qQDmcjOYn+vTJz/BNMUmGzQG0Yq/diRlDGMh93s/Li58Ysq7?= =?us-ascii?Q?8bNpGzJlGWZ9ymK1Y/cuMGCGeKeHwYLmA1nU3CqBAXR3F+gz/91qbWhe8ryq?= =?us-ascii?Q?9xH4uJf7e3niKzgbHj5Ugfd18bXpg2DU8mEmfin4llTQXUPM0DWIKZJZmj0x?= =?us-ascii?Q?F8c/25s64BpJC4kdW4K+Vc5wzvruuWJpC1GNYnQVoA3lqKDCVSN8BPmzX/Rt?= =?us-ascii?Q?2PhpnDXVBjFkLO0DuoybMDGt5gVvscDB6IrUxMdTKyARTvfTCfRVzBLUUxCk?= =?us-ascii?Q?PaCOOS58iIAdm103FBk9hIDnd3INucXlpKgzqFAikEUZy9lRttkORdzSytUy?= =?us-ascii?Q?99dMIe1oxmDAmxEj0DHnF5LBh4aGBeK9UpqdYwEYQ/aK/oc2OX4ZtZFV22Pz?= =?us-ascii?Q?gp1avf1vM4vI7ihqhkznrWiHGZeYlmyjDzkG7n3+szqdAtHQUZ0Ewog0iAGJ?= =?us-ascii?Q?fo2SMi77ZBH5XJuDDswVDuDhUIu24bqjAhA2ugzMq/zINvZvP9aK/LGNbXsD?= =?us-ascii?Q?dUSftJTa3xB/ry584V7jN+Pi8KTp16YwsVQ4fGasOKb0TrbBztPUhmC3aTsq?= =?us-ascii?Q?gts9sRdUHJ1fx1gsSXTRBcGI06MnpXJd7P8anwKSMNLl1EQCBpbwVPLGlsFq?= =?us-ascii?Q?utUEVMNvwvjuJxZEvvgVIltUR3B0swpr8im7Po2GhuGQxJNxq7rHV782AQV7?= =?us-ascii?Q?zRGkb1Rpl0tPmkwpPMZAIr8MeyXyyIGVD3rhhOdpN0j0rKeuI0KL9a/z9QPj?= =?us-ascii?Q?t5ws4o9zOYFlE9a9X+dervWofvPZaJEWy5OfXPMuO9npK3U//amN86facg6k?= =?us-ascii?Q?Mc06uST3Y90jVJAI3XKOGOzR9GVHFwGWUylK+uNVArRqLFcYcGeqyomuOmvN?= =?us-ascii?Q?pZREVSQ5Z7mlmYGv+h3126b/ktCyoAB2di/MKy/sRIrlR3QENKtumCgVrTwA?= =?us-ascii?Q?TvYixZ2SI6zMT2iaxtpF7M1tix7bmBGJxsIcoO9YaJ1AuSjOeXmor7MNMpV4?= =?us-ascii?Q?Z+WICtElKYAwQ+VIDkRLhvusBxo9IJ59UqSM3R5A6NhSSARvXOzZ9tRKR7x6?= =?us-ascii?Q?xjGHLXMXlAj4Iez4hJhI9IbOLiu/NZZb3Zv8J2TiTG2+kpmolOSNy086jK6l?= =?us-ascii?Q?SDW5eQPjH9V4sdX6lTahqIv8V0zBjf8wrtakfqnzdsdXgGR8yKb/GNnncBEv?= =?us-ascii?Q?rdnpjsI02AiygzZ4tcBrS8rVnUeLQrbL8dk5BtMgyJTxs5PbMo3Tzif4iTl1?= =?us-ascii?Q?3T/m/U7o9+ixBG8RTg6de+cXNSL3QFJHD4jRoKlnENtzaWQtBwzAYeCrVkHc?= =?us-ascii?Q?8TmmxBez5BdzhZSptyeuEi2s2Pbn0oiixV3fwrnbw7Ch9x/m0+Pc2/Yadytq?= =?us-ascii?Q?mi48pvWv5CFTZ32HPAQXYTaj8BxiNZj9UR3b9dHpnruF+ASl7Z9fKVLLZNVc?= =?us-ascii?Q?frJkjoz/qd7yeymdVaGMqD7GLnHLC6w9qHg4knWKV3pktvUtgwDWoOk8t4IE?= =?us-ascii?Q?z/Dk5xLTXwXbHGhPwPpNgGgOArKGKUcq9hLse+XPQgYJhrROJtqM7/bDu2Bv?= =?us-ascii?Q?2jPioJv9ULT8ItsqVzZ4KuL9D7hFXil5tjQQC14HDhXCZ4K0eAH70VuhCBXA?= =?us-ascii?Q?iKkh+KgSbw=3D=3D?= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: DM6PR11MB3530.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: c94db666-8722-4c29-f92f-08da482f649c X-MS-Exchange-CrossTenant-originalarrivaltime: 07 Jun 2022 02:42:41.4862 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 4n5m51NzSBa0zZcNYIA4jb0sjauiKzSPMmZ3HL9Eg76U3YQyoZk9ckbsuJT8gc5HbSxegJ5ei7rPtT1UDwF20A== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR11MB5970 X-OriginatorOrg: intel.com X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org > -----Original Message----- > From: Zhang, Tianfei > Sent: Monday, June 6, 2022 09:41 > To: Huang, Wei ; dev@dpdk.org; > thomas@monjalon.net; nipun.gupta@nxp.com; hemant.agrawal@nxp.com > Cc: stable@dpdk.org; Xu, Rosen ; Zhang, Qi Z > > Subject: RE: [PATCH v5 3/5] raw/afu_mf: add HE-LBK AFU driver >=20 >=20 >=20 > > -----Original Message----- > > From: Huang, Wei > > Sent: Friday, May 27, 2022 1:37 PM > > To: dev@dpdk.org; thomas@monjalon.net; nipun.gupta@nxp.com; > > hemant.agrawal@nxp.com > > Cc: stable@dpdk.org; Xu, Rosen ; Zhang, Tianfei > > ; Zhang, Qi Z ; Huang, > > Wei > > Subject: [PATCH v5 3/5] raw/afu_mf: add HE-LBK AFU driver > > > > HE-LBK and HE-MEM-LBK are host exerciser modules in OFS FPGA, HE-LBK > > is used to test PCI bus and HE-MEM-LBK is used to test local memory. > > This driver initialize the modules and report test result. > > > > Signed-off-by: Wei Huang > > --- > > drivers/raw/afu_mf/afu_mf_rawdev.c | 5 + > > drivers/raw/afu_mf/he_lbk.c | 427 > > +++++++++++++++++++++++++++++++++++++ > > drivers/raw/afu_mf/he_lbk.h | 121 +++++++++++ > > drivers/raw/afu_mf/meson.build | 2 +- > > drivers/raw/afu_mf/rte_pmd_afu.h | 14 ++ > > 5 files changed, 568 insertions(+), 1 deletion(-) create mode 100644 > > drivers/raw/afu_mf/he_lbk.c create mode 100644 > > drivers/raw/afu_mf/he_lbk.h > > > > diff --git a/drivers/raw/afu_mf/afu_mf_rawdev.c > > b/drivers/raw/afu_mf/afu_mf_rawdev.c > > index 7c18f3b..e91eb21 100644 > > --- a/drivers/raw/afu_mf/afu_mf_rawdev.c > > +++ b/drivers/raw/afu_mf/afu_mf_rawdev.c > > @@ -20,16 +20,21 @@ > > #include "rte_pmd_afu.h" > > #include "afu_mf_rawdev.h" > > #include "n3000_afu.h" > > +#include "he_lbk.h" > > > > #define AFU_MF_PMD_RAWDEV_NAME rawdev_afu_mf > > > > static const struct rte_afu_uuid afu_uuid_map[] =3D { > > { N3000_AFU_UUID_L, N3000_AFU_UUID_H }, > > + { HE_LBK_UUID_L, HE_LBK_UUID_H }, > > + { HE_MEM_LBK_UUID_L, HE_MEM_LBK_UUID_H }, > > { 0, 0 /* sentinel */ } > > }; > > > > static struct afu_mf_drv *afu_table[] =3D { > > &n3000_afu_drv, > > + &he_lbk_drv, > > + &he_mem_lbk_drv, > > NULL > > }; > > > > diff --git a/drivers/raw/afu_mf/he_lbk.c b/drivers/raw/afu_mf/he_lbk.c > > new file mode 100644 index 0000000..8735647 > > --- /dev/null > > +++ b/drivers/raw/afu_mf/he_lbk.c > > @@ -0,0 +1,427 @@ > > +/* SPDX-License-Identifier: BSD-3-Clause > > + * Copyright(c) 2022 Intel Corporation */ > > + > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > + > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > + > > +#include "afu_mf_rawdev.h" > > +#include "he_lbk.h" > > + > > +static int he_lbk_afu_config(struct afu_mf_rawdev *dev) { > > + struct he_lbk_priv *priv =3D NULL; > > + struct rte_pmd_afu_he_lbk_cfg *cfg =3D NULL; > > + struct he_lbk_csr_cfg v; > > + > > + if (!dev) > > + return -EINVAL; > > + > > + priv =3D (struct he_lbk_priv *)dev->priv; > > + if (!priv) > > + return -ENOENT; > > + > > + cfg =3D &priv->he_lbk_cfg; > > + > > + v.csr =3D 0; > > + > > + if (cfg->cont) > > + v.cont =3D 1; > > + > > + v.mode =3D cfg->mode; > > + v.trput_interleave =3D cfg->trput_interleave; > > + if (cfg->multi_cl =3D=3D 4) > > + v.multicl_len =3D 2; > > + else > > + v.multicl_len =3D cfg->multi_cl - 1; > > + > > + AFU_MF_PMD_DEBUG("cfg: 0x%08x", v.csr); > > + rte_write32(v.csr, priv->he_lbk_ctx.addr + CSR_CFG); > > + > > + return 0; > > +} > > + > > +static void he_lbk_report(struct afu_mf_rawdev *dev, uint32_t cl) { > > + struct he_lbk_priv *priv =3D NULL; > > + struct rte_pmd_afu_he_lbk_cfg *cfg =3D NULL; > > + struct he_lbk_ctx *ctx =3D NULL; > > + struct he_lbk_dsm_status *stat =3D NULL; > > + struct he_lbk_status0 stat0; > > + struct he_lbk_status1 stat1; > > + uint64_t swtest_msg =3D 0; > > + uint64_t ticks =3D 0; > > + uint64_t info =3D 0; > > + double num, rd_bw, wr_bw; > > + > > + if (!dev || !dev->priv) > > + return; > > + > > + priv =3D (struct he_lbk_priv *)dev->priv; > > + cfg =3D &priv->he_lbk_cfg; > > + ctx =3D &priv->he_lbk_ctx; > > + > > + stat =3D ctx->status_ptr; > > + > > + swtest_msg =3D rte_read64(ctx->addr + CSR_SWTEST_MSG); > > + stat0.csr =3D rte_read64(ctx->addr + CSR_STATUS0); > > + stat1.csr =3D rte_read64(ctx->addr + CSR_STATUS1); > > + > > + if (cfg->cont) > > + ticks =3D stat->num_clocks - stat->start_overhead; > > + else > > + ticks =3D stat->num_clocks - > > + (stat->start_overhead + stat->end_overhead); > > + > > + if (cfg->freq_mhz =3D=3D 0) { > > + info =3D rte_read64(ctx->addr + CSR_HE_INFO0); > > + AFU_MF_PMD_INFO("API version: %"PRIx64, info >> 16); > > + cfg->freq_mhz =3D info & 0xffff; > > + if (cfg->freq_mhz =3D=3D 0) { > > + AFU_MF_PMD_INFO("Frequency of AFU clock is > > unknown." > > + " Assuming 350 MHz."); > > + cfg->freq_mhz =3D 350; > > + } > > + } > > + > > + num =3D (double)stat0.num_reads; > > + rd_bw =3D (num * CLS_TO_SIZE(1) * MHZ(cfg->freq_mhz)) / ticks; > > + num =3D (double)stat0.num_writes; > > + wr_bw =3D (num * CLS_TO_SIZE(1) * MHZ(cfg->freq_mhz)) / ticks; > > + > > + printf("Cachelines Read_Count Write_Count Pend_Read > Pend_Write " > > + "Clocks@%uMHz Rd_Bandwidth Wr_Bandwidth\n", > > + cfg->freq_mhz); > > + printf("%10u %10u %10u %10u %10u %12"PRIu64 > > + " %7.3f GB/s %7.3f GB/s\n", > > + cl, stat0.num_reads, stat0.num_writes, > > + stat1.num_pend_reads, stat1.num_pend_writes, > > + ticks, rd_bw / 1e9, wr_bw / 1e9); > > + printf("Test Message: 0x%"PRIx64"\n", swtest_msg); } > > + > > +static int he_lbk_test(struct afu_mf_rawdev *dev) { > > + struct he_lbk_priv *priv =3D NULL; > > + struct rte_pmd_afu_he_lbk_cfg *cfg =3D NULL; > > + struct he_lbk_ctx *ctx =3D NULL; > > + struct he_lbk_csr_ctl ctl; > > + uint32_t *ptr =3D NULL; > > + uint32_t i, j, cl, val =3D 0; > > + uint64_t sval =3D 0; > > + int ret =3D 0; > > + > > + if (!dev) > > + return -EINVAL; > > + > > + priv =3D (struct he_lbk_priv *)dev->priv; > > + if (!priv) > > + return -ENOENT; > > + > > + cfg =3D &priv->he_lbk_cfg; > > + ctx =3D &priv->he_lbk_ctx; > > + > > + ctl.csr =3D 0; > > + rte_write32(ctl.csr, ctx->addr + CSR_CTL); > > + rte_delay_us(1000); > > + ctl.reset =3D 1; > > + rte_write32(ctl.csr, ctx->addr + CSR_CTL); > > + > > + /* initialize DMA addresses */ > > + AFU_MF_PMD_DEBUG("src_addr: 0x%"PRIx64, ctx->src_iova); > > + rte_write64(SIZE_TO_CLS(ctx->src_iova), ctx->addr + > CSR_SRC_ADDR); > > + > > + AFU_MF_PMD_DEBUG("dst_addr: 0x%"PRIx64, ctx->dest_iova); > > + rte_write64(SIZE_TO_CLS(ctx->dest_iova), ctx->addr + > CSR_DST_ADDR); > > + > > + AFU_MF_PMD_DEBUG("dsm_addr: 0x%"PRIx64, ctx->dsm_iova); > > + rte_write32(SIZE_TO_CLS(ctx->dsm_iova), ctx->addr + > > CSR_AFU_DSM_BASEL); > > + rte_write32(SIZE_TO_CLS(ctx->dsm_iova) >> 32, > > + ctx->addr + CSR_AFU_DSM_BASEH); > > + > > + ret =3D he_lbk_afu_config(dev); > > + if (ret) > > + return ret; > > + > > + /* initialize src data */ > > + ptr =3D (uint32_t *)ctx->src_ptr; > > + j =3D CLS_TO_SIZE(cfg->end) >> 2; > > + for (i =3D 0; i < j; i++) > > + *ptr++ =3D i; > > + > > + /* start test */ > > + for (cl =3D cfg->begin; cl <=3D cfg->end; cl +=3D cfg->multi_cl) { > > + memset(ctx->dest_ptr, 0, CLS_TO_SIZE(cl)); > > + memset(ctx->dsm_ptr, 0, DSM_SIZE); > > + > > + ctl.csr =3D 0; > > + rte_write32(ctl.csr, ctx->addr + CSR_CTL); > > + rte_delay_us(1000); > > + ctl.reset =3D 1; > > + rte_write32(ctl.csr, ctx->addr + CSR_CTL); > > + > > + rte_write32(cl - 1, ctx->addr + CSR_NUM_LINES); > > + > > + ctl.start =3D 1; > > + rte_write32(ctl.csr, ctx->addr + CSR_CTL); > > + > > + if (cfg->cont) { > > + rte_delay_ms(cfg->timeout * 1000); > > + ctl.force_completion =3D 1; > > + rte_write32(ctl.csr, ctx->addr + CSR_CTL); > > + ret =3D dsm_poll_timeout(&ctx->status_ptr- > > >test_complete, > > + val, (val & 0x1) =3D=3D 1, DSM_POLL_INTERVAL, > > + DSM_TIMEOUT); > > + if (ret) { > > + printf("DSM poll timeout\n"); > > + goto end; > > + } > > + } else { > > + ret =3D dsm_poll_timeout(&ctx->status_ptr- > > >test_complete, > > + val, (val & 0x1) =3D=3D 1, DSM_POLL_INTERVAL, > > + DSM_TIMEOUT); > > + if (ret) { > > + printf("DSM poll timeout\n"); > > + goto end; > > + } > > + ctl.force_completion =3D 1; > > + rte_write32(ctl.csr, ctx->addr + CSR_CTL); > > + } > > + > > + he_lbk_report(dev, cl); > > + > > + i =3D 0; > > + while (i++ < 100) { > > + sval =3D rte_read64(ctx->addr + CSR_STATUS1); > > + if (sval =3D=3D 0) > > + break; > > + rte_delay_us(1000); > > + } > > + > > + if (cfg->mode =3D=3D NLB_MODE_LPBK) { > > + ptr =3D (uint32_t *)ctx->dest_ptr; > > + j =3D CLS_TO_SIZE(cl) >> 2; > > + for (i =3D 0; i < j; i++) { > > + if (*ptr++ !=3D i) { > > + AFU_MF_PMD_ERR("Data mismatch > @ > > %u", i); > > + break; > > + } > > + } > > + } > > + } > > + > > +end: > > + return 0; > > +} > > + > > +static int he_lbk_ctx_release(struct afu_mf_rawdev *dev) { > > + struct he_lbk_priv *priv =3D NULL; > > + struct he_lbk_ctx *ctx =3D NULL; > > + > > + if (!dev) > > + return -EINVAL; > > + > > + priv =3D (struct he_lbk_priv *)dev->priv; > > + if (!priv) > > + return -ENOENT; > > + > > + ctx =3D &priv->he_lbk_ctx; > > + > > + rte_free(ctx->dsm_ptr); > > + ctx->dsm_ptr =3D NULL; > > + ctx->status_ptr =3D NULL; > > + > > + rte_free(ctx->src_ptr); > > + ctx->src_ptr =3D NULL; > > + > > + rte_free(ctx->dest_ptr); > > + ctx->dest_ptr =3D NULL; > > + > > + return 0; > > +} > > + > > +static int he_lbk_ctx_init(struct afu_mf_rawdev *dev) { > > + struct he_lbk_priv *priv =3D NULL; > > + struct he_lbk_ctx *ctx =3D NULL; > > + int ret =3D 0; > > + > > + if (!dev) > > + return -EINVAL; > > + > > + priv =3D (struct he_lbk_priv *)dev->priv; > > + if (!priv) > > + return -ENOENT; > > + > > + ctx =3D &priv->he_lbk_ctx; > > + ctx->addr =3D (uint8_t *)dev->addr; > > + > > + ctx->dsm_ptr =3D (uint8_t *)rte_zmalloc(NULL, DSM_SIZE, > > TEST_MEM_ALIGN); > > + if (!ctx->dsm_ptr) { > > + ret =3D -ENOMEM; > > + goto release; > > + } > > + ctx->dsm_iova =3D rte_malloc_virt2iova(ctx->dsm_ptr); > > + if (ctx->dsm_iova =3D=3D RTE_BAD_IOVA) { > > + ret =3D -ENOMEM; > > + goto release; > > + } > > + > > + ctx->src_ptr =3D (uint8_t *)rte_zmalloc(NULL, NLB_BUF_SIZE, > > + TEST_MEM_ALIGN); > > + if (!ctx->src_ptr) { > > + ret =3D -ENOMEM; > > + goto release; >=20 > If ctx->src_ptr alloc fail, he_lbk_ctx_release() can work? >=20 He_lbk_ctx_release() can work correct in failure situation, but it's not st= andard exception handle, I will change it. > > + } > > + ctx->src_iova =3D rte_malloc_virt2iova(ctx->src_ptr); > > + if (ctx->src_iova =3D=3D RTE_BAD_IOVA) { > > + ret =3D -ENOMEM; > > + goto release; > > + } > > + > > + ctx->dest_ptr =3D (uint8_t *)rte_zmalloc(NULL, NLB_BUF_SIZE, > > + TEST_MEM_ALIGN); > > + if (!ctx->dest_ptr) { > > + ret =3D -ENOMEM; > > + goto release; > > + } > > + ctx->dest_iova =3D rte_malloc_virt2iova(ctx->dest_ptr); > > + if (ctx->dest_iova =3D=3D RTE_BAD_IOVA) { > > + ret =3D -ENOMEM; > > + goto release; > > + } > > + > > + ctx->status_ptr =3D (struct he_lbk_dsm_status *)ctx->dsm_ptr; > > + return 0; > > + > > +release: > > + he_lbk_ctx_release(dev); > > + return ret; > > +} > > + > > +static int he_lbk_init(struct afu_mf_rawdev *dev) { > > + if (!dev) > > + return -EINVAL; > > + > > + if (!dev->priv) { > > + dev->priv =3D rte_zmalloc(NULL, sizeof(struct he_lbk_priv), 0); > > + if (!dev->priv) > > + return -ENOMEM; > > + } > > + > > + return he_lbk_ctx_init(dev); > > +} > > + > > +static int he_lbk_config(struct afu_mf_rawdev *dev, void *config, > > + size_t config_size) > > +{ > > + struct he_lbk_priv *priv =3D NULL; > > + struct rte_pmd_afu_he_lbk_cfg *cfg =3D NULL; > > + > > + if (!dev || !config || !config_size) > > + return -EINVAL; > > + > > + priv =3D (struct he_lbk_priv *)dev->priv; > > + if (!priv) > > + return -ENOENT; > > + > > + if (config_size !=3D sizeof(struct rte_pmd_afu_he_lbk_cfg)) > > + return -EINVAL; > > + > > + cfg =3D (struct rte_pmd_afu_he_lbk_cfg *)config; > > + if (cfg->mode > NLB_MODE_TRPUT) > > + return -EINVAL; > > + if ((cfg->multi_cl !=3D 1) && (cfg->multi_cl !=3D 2) && > > + (cfg->multi_cl !=3D 4)) > > + return -EINVAL; > > + if ((cfg->begin < MIN_CACHE_LINES) || (cfg->begin > > > MAX_CACHE_LINES)) > > + return -EINVAL; > > + if ((cfg->end < cfg->begin) || (cfg->end > MAX_CACHE_LINES)) > > + return -EINVAL; > > + > > + rte_memcpy(&priv->he_lbk_cfg, cfg, sizeof(priv->he_lbk_cfg)); > > + > > + return 0; > > +} > > + > > +static int he_lbk_close(struct afu_mf_rawdev *dev) { > > + if (!dev) > > + return -EINVAL; > > + > > + he_lbk_ctx_release(dev); > > + > > + rte_free(dev->priv); > > + dev->priv =3D NULL; > > + > > + return 0; > > +} > > + > > +static int he_lbk_dump(struct afu_mf_rawdev *dev, FILE *f) { > > + struct he_lbk_priv *priv =3D NULL; > > + struct he_lbk_ctx *ctx =3D NULL; > > + > > + if (!dev) > > + return -EINVAL; > > + > > + priv =3D (struct he_lbk_priv *)dev->priv; > > + if (!priv) > > + return -ENOENT; > > + > > + if (!f) > > + f =3D stdout; > > + > > + ctx =3D &priv->he_lbk_ctx; > > + > > + fprintf(f, "addr:\t\t%p\n", (void *)ctx->addr); > > + fprintf(f, "dsm_ptr:\t%p\n", (void *)ctx->dsm_ptr); > > + fprintf(f, "dsm_iova:\t0x%"PRIx64"\n", ctx->dsm_iova); > > + fprintf(f, "src_ptr:\t%p\n", (void *)ctx->src_ptr); > > + fprintf(f, "src_iova:\t0x%"PRIx64"\n", ctx->src_iova); > > + fprintf(f, "dest_ptr:\t%p\n", (void *)ctx->dest_ptr); > > + fprintf(f, "dest_iova:\t0x%"PRIx64"\n", ctx->dest_iova); > > + fprintf(f, "status_ptr:\t%p\n", (void *)ctx->status_ptr); > > + > > + return 0; > > +} > > + > > +static struct afu_mf_ops he_lbk_ops =3D { > > + .init =3D he_lbk_init, > > + .config =3D he_lbk_config, > > + .start =3D NULL, > > + .stop =3D NULL, > > + .test =3D he_lbk_test, > > + .close =3D he_lbk_close, > > + .dump =3D he_lbk_dump, > > + .reset =3D NULL > > +}; > > + > > +struct afu_mf_drv he_lbk_drv =3D { > > + .uuid =3D { HE_LBK_UUID_L, HE_LBK_UUID_H }, > > + .ops =3D &he_lbk_ops > > +}; > > + > > +struct afu_mf_drv he_mem_lbk_drv =3D { > > + .uuid =3D { HE_MEM_LBK_UUID_L, HE_MEM_LBK_UUID_H }, > > + .ops =3D &he_lbk_ops > > +}; > > diff --git a/drivers/raw/afu_mf/he_lbk.h b/drivers/raw/afu_mf/he_lbk.h > > new file mode 100644 index 0000000..c2e8a29 > > --- /dev/null > > +++ b/drivers/raw/afu_mf/he_lbk.h > > @@ -0,0 +1,121 @@ > > +/* SPDX-License-Identifier: BSD-3-Clause > > + * Copyright(c) 2022 Intel Corporation */ > > + > > +#ifndef _HE_LBK_H_ > > +#define _HE_LBK_H_ > > + > > +#include "afu_mf_rawdev.h" > > +#include "rte_pmd_afu.h" > > + > > +#define HE_LBK_UUID_L 0xb94b12284c31e02b > > +#define HE_LBK_UUID_H 0x56e203e9864f49a7 > > +#define HE_MEM_LBK_UUID_L 0xbb652a578330a8eb #define > > HE_MEM_LBK_UUID_H > > +0x8568ab4e6ba54616 > > + > > +extern struct afu_mf_drv he_lbk_drv; > > +extern struct afu_mf_drv he_mem_lbk_drv; > > + > > +/* HE-LBK & HE-MEM-LBK registers definition */ > > +#define CSR_SCRATCHPAD0 0x100 > > +#define CSR_SCRATCHPAD1 0x108 > > +#define CSR_AFU_DSM_BASEL 0x110 > > +#define CSR_AFU_DSM_BASEH 0x114 > > +#define CSR_SRC_ADDR 0x120 > > +#define CSR_DST_ADDR 0x128 > > +#define CSR_NUM_LINES 0x130 > > +#define CSR_CTL 0x138 > > +#define CSR_CFG 0x140 > > +#define CSR_INACT_THRESH 0x148 > > +#define CSR_INTERRUPT0 0x150 > > +#define CSR_SWTEST_MSG 0x158 > > +#define CSR_STATUS0 0x160 > > +#define CSR_STATUS1 0x168 > > +#define CSR_ERROR 0x170 > > +#define CSR_STRIDE 0x178 > > +#define CSR_HE_INFO0 0x180 > > + > > +#define DSM_SIZE 0x200000 > > +#define DSM_POLL_INTERVAL 5 /* ms */ > > +#define DSM_TIMEOUT 1000 /* ms */ > > + > > +#define NLB_BUF_SIZE 0x400000 > > +#define TEST_MEM_ALIGN 1024 > > + > > +struct he_lbk_csr_ctl { > > + union { > > + uint32_t csr; > > + struct { > > + uint32_t reset:1; > > + uint32_t start:1; > > + uint32_t force_completion:1; > > + uint32_t reserved:29; > > + }; > > + }; > > +}; > > + > > +struct he_lbk_csr_cfg { > > + union { > > + uint32_t csr; > > + struct { > > + uint32_t rsvd1:1; > > + uint32_t cont:1; > > + uint32_t mode:3; > > + uint32_t multicl_len:2; > > + uint32_t rsvd2:13; > > + uint32_t trput_interleave:3; > > + uint32_t test_cfg:5; > > + uint32_t interrupt_on_error:1; > > + uint32_t interrupt_testmode:1; > > + uint32_t rsvd3:2; > > + }; > > + }; > > +}; > > + > > +struct he_lbk_status0 { > > + union { > > + uint64_t csr; > > + struct { > > + uint32_t num_writes; > > + uint32_t num_reads; > > + }; > > + }; > > +}; > > + > > +struct he_lbk_status1 { > > + union { > > + uint64_t csr; > > + struct { > > + uint32_t num_pend_writes; > > + uint32_t num_pend_reads; > > + }; > > + }; > > +}; > > + > > +struct he_lbk_dsm_status { > > + uint32_t test_complete; > > + uint32_t test_error; > > + uint64_t num_clocks; > > + uint32_t num_reads; > > + uint32_t num_writes; > > + uint32_t start_overhead; > > + uint32_t end_overhead; > > +}; > > + > > +struct he_lbk_ctx { > > + uint8_t *addr; > > + uint8_t *dsm_ptr; > > + uint64_t dsm_iova; > > + uint8_t *src_ptr; > > + uint64_t src_iova; > > + uint8_t *dest_ptr; > > + uint64_t dest_iova; > > + struct he_lbk_dsm_status *status_ptr; }; > > + > > +struct he_lbk_priv { > > + struct rte_pmd_afu_he_lbk_cfg he_lbk_cfg; > > + struct he_lbk_ctx he_lbk_ctx; > > +}; > > + > > +#endif /* _HE_LBK_H_ */ > > diff --git a/drivers/raw/afu_mf/meson.build > > b/drivers/raw/afu_mf/meson.build index 8a989e3..a983f53 100644 > > --- a/drivers/raw/afu_mf/meson.build > > +++ b/drivers/raw/afu_mf/meson.build > > @@ -2,6 +2,6 @@ > > # Copyright 2022 Intel Corporation > > > > deps +=3D ['rawdev', 'bus_pci', 'bus_ifpga'] -sources =3D > > files('afu_mf_rawdev.c', > > 'n3000_afu.c') > > +sources =3D files('afu_mf_rawdev.c', 'n3000_afu.c', 'he_lbk.c') > > > > headers =3D files('rte_pmd_afu.h') > > diff --git a/drivers/raw/afu_mf/rte_pmd_afu.h > > b/drivers/raw/afu_mf/rte_pmd_afu.h > > index f14a053..658df55 100644 > > --- a/drivers/raw/afu_mf/rte_pmd_afu.h > > +++ b/drivers/raw/afu_mf/rte_pmd_afu.h > > @@ -90,6 +90,20 @@ struct rte_pmd_afu_n3000_cfg { > > }; > > }; > > > > +/** > > + * HE-LBK & HE-MEM-LBK AFU configuration data structure. > > + */ > > +struct rte_pmd_afu_he_lbk_cfg { > > + uint32_t mode; > > + uint32_t begin; > > + uint32_t end; > > + uint32_t multi_cl; > > + uint32_t cont; > > + uint32_t timeout; > > + uint32_t trput_interleave; > > + uint32_t freq_mhz; > > +}; > > + > > #ifdef __cplusplus > > } > > #endif > > -- > > 1.8.3.1