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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: DM6PR11MB4491.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: fe6a4671-bf02-4d1d-158b-08d994af5249 X-MS-Exchange-CrossTenant-originalarrivaltime: 21 Oct 2021 16:24:56.8885 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: konstantin.ananyev@intel.com X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR11MB3578 X-OriginatorOrg: intel.com Subject: Re: [dpdk-dev] [PATCH v4 1/5] eal: add new definitions for wait scheme X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > Introduce macros as generic interface for address monitoring. >=20 > Signed-off-by: Feifei Wang > Reviewed-by: Ruifeng Wang > --- > lib/eal/arm/include/rte_pause_64.h | 126 ++++++++++++++++------------ > lib/eal/include/generic/rte_pause.h | 32 +++++++ > 2 files changed, 104 insertions(+), 54 deletions(-) >=20 > diff --git a/lib/eal/arm/include/rte_pause_64.h b/lib/eal/arm/include/rte= _pause_64.h > index e87d10b8cc..23954c2de2 100644 > --- a/lib/eal/arm/include/rte_pause_64.h > +++ b/lib/eal/arm/include/rte_pause_64.h > @@ -31,20 +31,12 @@ static inline void rte_pause(void) > /* Put processor into low power WFE(Wait For Event) state. */ > #define __WFE() { asm volatile("wfe" : : : "memory"); } >=20 > -static __rte_always_inline void > -rte_wait_until_equal_16(volatile uint16_t *addr, uint16_t expected, > - int memorder) > -{ > - uint16_t value; > - > - assert(memorder =3D=3D __ATOMIC_ACQUIRE || memorder =3D=3D __ATOMIC_REL= AXED); > - > - /* > - * Atomic exclusive load from addr, it returns the 16-bit content of > - * *addr while making it 'monitored',when it is written by someone > - * else, the 'monitored' state is cleared and a event is generated > - * implicitly to exit WFE. > - */ > +/* > + * Atomic exclusive load from addr, it returns the 16-bit content of > + * *addr while making it 'monitored', when it is written by someone > + * else, the 'monitored' state is cleared and a event is generated > + * implicitly to exit WFE. > + */ > #define __LOAD_EXC_16(src, dst, memorder) { \ > if (memorder =3D=3D __ATOMIC_RELAXED) { \ > asm volatile("ldxrh %w[tmp], [%x[addr]]" \ > @@ -58,6 +50,52 @@ rte_wait_until_equal_16(volatile uint16_t *addr, uint1= 6_t expected, > : "memory"); \ > } } >=20 > +/* > + * Atomic exclusive load from addr, it returns the 32-bit content of > + * *addr while making it 'monitored', when it is written by someone > + * else, the 'monitored' state is cleared and a event is generated > + * implicitly to exit WFE. > + */ > +#define __LOAD_EXC_32(src, dst, memorder) { \ > + if (memorder =3D=3D __ATOMIC_RELAXED) { \ > + asm volatile("ldxr %w[tmp], [%x[addr]]" \ > + : [tmp] "=3D&r" (dst) \ > + : [addr] "r"(src) \ > + : "memory"); \ > + } else { \ > + asm volatile("ldaxr %w[tmp], [%x[addr]]" \ > + : [tmp] "=3D&r" (dst) \ > + : [addr] "r"(src) \ > + : "memory"); \ > + } } > + > +/* > + * Atomic exclusive load from addr, it returns the 64-bit content of > + * *addr while making it 'monitored', when it is written by someone > + * else, the 'monitored' state is cleared and a event is generated > + * implicitly to exit WFE. > + */ > +#define __LOAD_EXC_64(src, dst, memorder) { \ > + if (memorder =3D=3D __ATOMIC_RELAXED) { \ > + asm volatile("ldxr %x[tmp], [%x[addr]]" \ > + : [tmp] "=3D&r" (dst) \ > + : [addr] "r"(src) \ > + : "memory"); \ > + } else { \ > + asm volatile("ldaxr %x[tmp], [%x[addr]]" \ > + : [tmp] "=3D&r" (dst) \ > + : [addr] "r"(src) \ > + : "memory"); \ > + } } > + > +static __rte_always_inline void > +rte_wait_until_equal_16(volatile uint16_t *addr, uint16_t expected, > + int memorder) > +{ > + uint16_t value; > + > + assert(memorder =3D=3D __ATOMIC_ACQUIRE || memorder =3D=3D __ATOMIC_REL= AXED); > + > __LOAD_EXC_16(addr, value, memorder) > if (value !=3D expected) { > __SEVL() > @@ -66,7 +104,6 @@ rte_wait_until_equal_16(volatile uint16_t *addr, uint1= 6_t expected, > __LOAD_EXC_16(addr, value, memorder) > } while (value !=3D expected); > } > -#undef __LOAD_EXC_16 > } >=20 > static __rte_always_inline void > @@ -77,25 +114,6 @@ rte_wait_until_equal_32(volatile uint32_t *addr, uint= 32_t expected, >=20 > assert(memorder =3D=3D __ATOMIC_ACQUIRE || memorder =3D=3D __ATOMIC_REL= AXED); >=20 > - /* > - * Atomic exclusive load from addr, it returns the 32-bit content of > - * *addr while making it 'monitored',when it is written by someone > - * else, the 'monitored' state is cleared and a event is generated > - * implicitly to exit WFE. > - */ > -#define __LOAD_EXC_32(src, dst, memorder) { \ > - if (memorder =3D=3D __ATOMIC_RELAXED) { \ > - asm volatile("ldxr %w[tmp], [%x[addr]]" \ > - : [tmp] "=3D&r" (dst) \ > - : [addr] "r"(src) \ > - : "memory"); \ > - } else { \ > - asm volatile("ldaxr %w[tmp], [%x[addr]]" \ > - : [tmp] "=3D&r" (dst) \ > - : [addr] "r"(src) \ > - : "memory"); \ > - } } > - > __LOAD_EXC_32(addr, value, memorder) > if (value !=3D expected) { > __SEVL() > @@ -104,7 +122,6 @@ rte_wait_until_equal_32(volatile uint32_t *addr, uint= 32_t expected, > __LOAD_EXC_32(addr, value, memorder) > } while (value !=3D expected); > } > -#undef __LOAD_EXC_32 > } >=20 > static __rte_always_inline void > @@ -115,25 +132,6 @@ rte_wait_until_equal_64(volatile uint64_t *addr, uin= t64_t expected, >=20 > assert(memorder =3D=3D __ATOMIC_ACQUIRE || memorder =3D=3D __ATOMIC_REL= AXED); >=20 > - /* > - * Atomic exclusive load from addr, it returns the 64-bit content of > - * *addr while making it 'monitored',when it is written by someone > - * else, the 'monitored' state is cleared and a event is generated > - * implicitly to exit WFE. > - */ > -#define __LOAD_EXC_64(src, dst, memorder) { \ > - if (memorder =3D=3D __ATOMIC_RELAXED) { \ > - asm volatile("ldxr %x[tmp], [%x[addr]]" \ > - : [tmp] "=3D&r" (dst) \ > - : [addr] "r"(src) \ > - : "memory"); \ > - } else { \ > - asm volatile("ldaxr %x[tmp], [%x[addr]]" \ > - : [tmp] "=3D&r" (dst) \ > - : [addr] "r"(src) \ > - : "memory"); \ > - } } > - > __LOAD_EXC_64(addr, value, memorder) > if (value !=3D expected) { > __SEVL() > @@ -143,6 +141,26 @@ rte_wait_until_equal_64(volatile uint64_t *addr, uin= t64_t expected, > } while (value !=3D expected); > } > } > + > +#define rte_wait_event(addr, mask, expected, cond, memorder, size) \ > +do { \ > + RTE_BUILD_BUG_ON(!__builtin_constant_p(memorder)); \ > + RTE_BUILD_BUG_ON(memorder !=3D __ATOMIC_ACQUIRE && \ > + memorder !=3D __ATOMIC_RELAXED); \ > + RTE_BUILD_BUG_ON(size !=3D 16 && size !=3D 32 && size !=3D 64); \ > + uint##size_t value; \ > + __LOAD_EXC_##size(addr, value, memorder) \ > + if ((value & mask) cond expected) { \ > + __SEVL() \ > + do { \ > + __WFE() \ > + __LOAD_EXC_##size(addr, value, memorder) \ > + } while ((value & mask) cond expected); \ > + } \ > +} while (0) > + > +#undef __LOAD_EXC_16 > +#undef __LOAD_EXC_32 > #undef __LOAD_EXC_64 >=20 > #undef __SEVL > diff --git a/lib/eal/include/generic/rte_pause.h b/lib/eal/include/generi= c/rte_pause.h > index 668ee4a184..20a5d2a9fd 100644 > --- a/lib/eal/include/generic/rte_pause.h > +++ b/lib/eal/include/generic/rte_pause.h > @@ -111,6 +111,38 @@ rte_wait_until_equal_64(volatile uint64_t *addr, uin= t64_t expected, > while (__atomic_load_n(addr, memorder) !=3D expected) > rte_pause(); > } > + > +/* > + * Wait until *addr breaks the condition, with a relaxed memory > + * ordering model meaning the loads around this API can be reordered. > + * > + * @param addr > + * A pointer to the memory location. > + * @param mask > + * A mask of value bits in interest. > + * @param expected > + * A 16-bit expected value to be in the memory location. > + * @param cond > + * A symbol representing the condition (=3D=3D, !=3D). > + * @param memorder > + * Two different memory orders that can be specified: > + * __ATOMIC_ACQUIRE and __ATOMIC_RELAXED. These map to > + * C++11 memory orders with the same names, see the C++11 standard or > + * the GCC wiki on atomic synchronization for detailed definition. > + * @param size > + * The bit size of *addr: > + * It is used for arm architecture to choose load instructions, > + * and the optional value is 16, 32 and 64. > + */ > +#define rte_wait_event(addr, mask, expected, cond, memorder, size) \ > +do { \ > + RTE_BUILD_BUG_ON(!__builtin_constant_p(memorder)); \ > + RTE_BUILD_BUG_ON(memorder !=3D __ATOMIC_ACQUIRE && \ > + memorder !=3D __ATOMIC_RELAXED); \ > + RTE_BUILD_BUG_ON(size !=3D 16 && size !=3D 32 && size !=3D 64); \ I don't' really understand why you do need 'size' passed as parameter. Can't it be: size_t size =3D sizeof(*(addr)); And then: RTE_BUILD_BUG_ON(size !=3D sizeof(uint16_t) && size !=3D sizeof(uint32_t) &= & size !=3D sizeof(uint64_t)); =20 ? > + while ((__atomic_load_n(addr, memorder) & mask) cond expected) \ > + rte_pause(); \ Just to repeat my own comment from previous version review:=20 put () around macro parameters in the macro body. Will save from a lot of unexpected troubles. > +} while (0) > #endif >=20 > #endif /* _RTE_PAUSE_H_ */ > -- > 2.25.1