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From: Raslan Darawsheh <rasland@nvidia.com>
To: Bing Zhao <bingz@nvidia.com>,
	Slava Ovsiienko <viacheslavo@nvidia.com>,
	Matan Azrad <matan@nvidia.com>
Cc: "dev@dpdk.org" <dev@dpdk.org>, Ori Kam <orika@nvidia.com>,
	"stable@dpdk.org" <stable@dpdk.org>
Subject: Re: [dpdk-dev] [PATCH] net/mlx5: fix the eCPRI common header endianness
Date: Thu, 5 Nov 2020 15:01:36 +0000
Message-ID: <DM6PR12MB274800D4C5363FA14CCED306CFEE0@DM6PR12MB2748.namprd12.prod.outlook.com> (raw)
In-Reply-To: <1604382118-336293-1-git-send-email-bingz@nvidia.com>

Hi,
> -----Original Message-----
> From: Bing Zhao <bingz@nvidia.com>
> Sent: Tuesday, November 3, 2020 7:42 AM
> To: Slava Ovsiienko <viacheslavo@nvidia.com>; Matan Azrad
> <matan@nvidia.com>
> Cc: dev@dpdk.org; Ori Kam <orika@nvidia.com>; Raslan Darawsheh
> <rasland@nvidia.com>; stable@dpdk.org
> Subject: [PATCH] net/mlx5: fix the eCPRI common header endianness
> 
> The input header of a RTE flow item is with network byte order. In
> the host with little endian, the bit field order are the same as the
> byte order.
> When checking the an eCPRI message type, the wrong field will be
> selected. Right now, since the whole u32 is being checked and for
> all types, the following implementation is unique. There is no
> functional risk but it is still an error to fix.
> 
> Fixes: daa38a8924a0 ("net/mlx5: add flow translation of eCPRI header")
> 
> Cc: stable@dpdk.org
> 
> Signed-off-by: Bing Zhao <bingz@nvidia.com>
> Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
> ---
>  drivers/net/mlx5/mlx5_flow_dv.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
Patch applied to next-net-mlx,

Kindest regards,
Raslan Darawsheh

  reply	other threads:[~2020-11-05 15:01 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-11-03  5:41 Bing Zhao
2020-11-05 15:01 ` Raslan Darawsheh [this message]
2020-11-06 11:19 ` Ferruh Yigit
2020-11-06 14:10   ` Bing Zhao
2020-11-06 17:41     ` Ferruh Yigit
2020-11-09  6:01       ` Bing Zhao

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