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From: Raslan Darawsheh <rasland@nvidia.com>
To: Alexander Kozyrev <akozyrev@nvidia.com>, "dev@dpdk.org" <dev@dpdk.org>
Cc: "stable@dpdk.org" <stable@dpdk.org>,
	Dekel Peled <dekelp@nvidia.com>, Matan Azrad <matan@nvidia.com>
Subject: Re: [dpdk-dev] [PATCH] net/mlx5: fix packet padding config for RxQ via DevX
Date: Tue, 17 Nov 2020 10:52:32 +0000	[thread overview]
Message-ID: <DM6PR12MB274886436FE9DE64EB7258D1CFE20@DM6PR12MB2748.namprd12.prod.outlook.com> (raw)
In-Reply-To: <20201115142534.31383-1-akozyrev@nvidia.com>


> -----Original Message-----
> From: Alexander Kozyrev <akozyrev@nvidia.com>
> Sent: Sunday, November 15, 2020 4:26 PM
> To: dev@dpdk.org
> Cc: stable@dpdk.org; Raslan Darawsheh <rasland@nvidia.com>; Dekel Peled
> <dekelp@nvidia.com>; Matan Azrad <matan@nvidia.com>
> Subject: [PATCH] net/mlx5: fix packet padding config for RxQ via DevX
> Received packets can be aligned to the size of the cache line on
> PCI transactions. This could improve performance by avoiding
> partial cache line writes in exchange for increased PCI bandwidth.
> This feature is supposed to be controlled by the rxq_pkt_pad_en
> devarg and it is true for an RxQ created via the Verbs API.
> But in the DevX API case, it is erroneously controlled by the
> rxq_cqe_pad_en devarg instead, which is in charge of the CQE
> padding instead and should not control the RxQ creation.
> Fix DevX RxQ creation by using the proper configuration flag for
> Rx packet padding that is being set by the rxq_pkt_pad_en devarg.
> Fixes: dc9ceff73c ("net/mlx5: create advanced RxQ via DevX")
> Cc: stable@dpdk.org
> Signed-off-by: Alexander Kozyrev <akozyrev@nvidia.com>
> Acked-by: Matan Azrad <matan@nvidia.com>

Patch applied to next-net-mlx,

Kindest regards,
Raslan Darawsheh

      reply	other threads:[~2020-11-17 10:52 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-11-15 14:25 Alexander Kozyrev
2020-11-17 10:52 ` Raslan Darawsheh [this message]

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