From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7102AA04C7; Mon, 14 Sep 2020 16:25:48 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 27C772BAB; Mon, 14 Sep 2020 16:25:48 +0200 (CEST) Received: from NAM04-BN3-obe.outbound.protection.outlook.com (mail-eopbgr680060.outbound.protection.outlook.com [40.107.68.60]) by dpdk.org (Postfix) with ESMTP id 75408FFA for ; Mon, 14 Sep 2020 16:25:46 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=hWwbd8dkPjDCu+71hdKUbcM7fLao0Z2qRtFXLzTv7UHGdDW1aGYUJuTMOZ8tmmDznBy3VErmb7+X5Ci6evrS6E7K/+CQqC/+I1Ilxkr3/KglDsjPYsiTjrnknfuk9CWeukTKNelj5QkTaL2qQD1pw5PBdqFOC2FUBEKc6csz9y3MHjdz622om3ubMEAlvA7rQHE3dGUYh7q6C2T1Imyiki26wEREepMyFWnZ1qFuNSdq9rnmgpaYjLsazzNtJdJlYzGWOjAR12JeDfGMCgTdPrhZ/x/xAJsfJH9WfPx7muqR+baNrV8i7hP8heqI09eX5oFN3kjHcgNOXdsnfCCkhQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=BVztqO8J9oczz2dc7uoKEgn+v54EF9WCmV1Xzqczob4=; b=HBLcO7kQ3lGG/i7uyZo89kSjrGPwLmSZFubshdm8uV/nQgxuxZvHA06Xb8IQyiSWADN1Y5GbcaDa32fTKsC4IYIk5rEWKvEHIe/gbNmT9bch9vSzn/5dDCb8fYgGYBw2KTlSFegrenOshwVnCRssRzfS8aMvffG3kHz2bpcTB6Yd+zJJT/jPciP/SiS5XwMzJiqAnVG6VDIfkDrnEkZKjykVcOrKQqul/ViU90M7dk4UrM1SIZ0q3GhdNpoPqqMnULsY+NIOh38WV4+Vk1RdVKZpw/WuBqV9BFBPXtAoc9umLdvqlEkyM+pSO262iGXXgMO4e5bMOB29jAOghAWjKA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=amd.com; dmarc=pass action=none header.from=amd.com; dkim=pass header.d=amd.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amdcloud.onmicrosoft.com; s=selector2-amdcloud-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=BVztqO8J9oczz2dc7uoKEgn+v54EF9WCmV1Xzqczob4=; b=3e/NExLfaBqZ4PDbH3SkgRs6BIDAn0r348F3WBEcYdOTIYMaG3wty9NpQ8oEHa8QhQrbq5u7USA4wUS1wO/7BMq5rQxjBVVkrqYN5P9BYsCmI1gGy+qoW+EfSG//PEo4MxYLys4yj0okw66psdEhAHrds69lsWVhI1HyLslCE8s= Received: from DM6PR12MB3628.namprd12.prod.outlook.com (2603:10b6:5:3d::26) by DM6PR12MB4233.namprd12.prod.outlook.com (2603:10b6:5:210::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3370.16; Mon, 14 Sep 2020 14:25:45 +0000 Received: from DM6PR12MB3628.namprd12.prod.outlook.com ([fe80::642e:e84f:76ba:5d14]) by DM6PR12MB3628.namprd12.prod.outlook.com ([fe80::642e:e84f:76ba:5d14%7]) with mapi id 15.20.3370.019; Mon, 14 Sep 2020 14:25:44 +0000 From: "Somalapuram, Amaranath" To: "Sebastian, Selwin" , "dev@dpdk.org" , Ferruh Yigit Thread-Topic: [PATCH v2] net/axgbe: enable IEEE 1588 PTP support Thread-Index: AQHWPnCpkMVwWtqLBk6U6/Ya5+T11KloyH8Q Date: Mon, 14 Sep 2020 14:25:44 +0000 Message-ID: References: <20200609151343.2097-1-selwin.sebastian@amd.com> In-Reply-To: <20200609151343.2097-1-selwin.sebastian@amd.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: msip_labels: MSIP_Label_76546daa-41b6-470c-bb85-f6f40f044d7f_ActionId=70be7ca6-295b-4833-a1b7-3f31fcb111d3; MSIP_Label_76546daa-41b6-470c-bb85-f6f40f044d7f_ContentBits=0; MSIP_Label_76546daa-41b6-470c-bb85-f6f40f044d7f_Enabled=true; MSIP_Label_76546daa-41b6-470c-bb85-f6f40f044d7f_Method=Standard; MSIP_Label_76546daa-41b6-470c-bb85-f6f40f044d7f_Name=Internal Use Only - Unrestricted; MSIP_Label_76546daa-41b6-470c-bb85-f6f40f044d7f_SetDate=2020-09-14T14:24:01Z; MSIP_Label_76546daa-41b6-470c-bb85-f6f40f044d7f_SiteId=3dd8961f-e488-4e60-8e11-a82d994e183d; authentication-results: amd.com; dkim=none (message not signed) header.d=none;amd.com; dmarc=none action=none header.from=amd.com; x-originating-ip: [2405:201:d805:faa:e1b6:164b:9828:d1aa] x-ms-publictraffictype: Email x-ms-office365-filtering-ht: Tenant x-ms-office365-filtering-correlation-id: e1cac4eb-93d7-4de8-fb91-08d858ba111f x-ms-traffictypediagnostic: DM6PR12MB4233: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:386; x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: 0bJ6J5D+d4c3DYtqdJ3E28mZNELTDPDx8DHEFj6idb5lT5SNdMgHWa6G+mTBBFwDacGi6LkC+iE+XR9KBE6hu6nL1NK0G5tr5RumbXIP2DlvIsvqViW7MLmPQyGMgmigqdopZl48wyT8QNbrDZXakr7INyP2AnFVwSt7s2qfUe2KgruJAhOILJlyEW3quqWVrivwaftGPVRzXRqnQD0n5aGM3Hin0uXqJc79AET34xwyIFTtXmcGVhNNQ5VW/GMxdnGCotHxwt3wAb+KCtyK75CXYBDGTcLTgV9lLJANmqt8pg9b2ItZFB/CjgyBw1Bg5Yd3NG2sN2g+HWt7JGLuNg== x-forefront-antispam-report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:DM6PR12MB3628.namprd12.prod.outlook.com; PTR:; CAT:NONE; SFS:(4636009)(39860400002)(136003)(396003)(366004)(376002)(346002)(7696005)(86362001)(9686003)(55016002)(30864003)(316002)(2906002)(186003)(33656002)(53546011)(76116006)(5660300002)(52536014)(71200400001)(6506007)(478600001)(110136005)(8936002)(8676002)(64756008)(66446008)(83380400001)(66476007)(66556008)(66946007); DIR:OUT; SFP:1101; x-ms-exchange-antispam-messagedata: W4Lc+kznibEQpr/sSw3M+SRMnJiyQCvOBRw512UEsCtit9DqZNwjFxFjdr3Deku5O7iRZhxlBWStUdTI6MPam4/s4w58Fe05q0p7+bM6slP/kH822h+dn7hEOls/hM28lWHTPj1tlwxGO5LNVbDwxfgn/GoLjJQJxsZkRD9podTjKC4WjOkYUrphVBfKwWCB4hz3OiaQZPLeRXqdeCNympIKu3VjclpNPkJ4+RiUFJ0SGM4NFXrw7wR6jTL3SgOdmTA+0QJLobhyfldqvE+udCiOQhgud0pJhRLiZFmQ+QFNx8oo1G0ZfY6iZzb1XcuwpYJklyzGqJlURd0G/PbMiv3nutPmxAb2vOiMazSMxKl1mb+LjvkRLZR6WjoNhRHj9QkK2z1CMl434m8yHh1zL48rlD/BmohCqw6f/Qv9mdeH2mLqO71pg5hypuNV+3oWtRgeylYiRoXPmkDWAHi7oY3g81iqq0YPS+2FrR2MrcUfY61kyLsx7MdOWbQ6Qd17o+qWlFCCAqqKg0YZiUBQVCR83NZN29ux2B/cFsqf0u7FeSF7b+Yj094khxEnAnidnI7HUrkduz30w3pnUNP9R3B8F7FgAZ0jBVRavv6ZdL0a64Nofq9poM+1QmR4GuomuK3tq6tUr7VcostCGSoUFFpCE1tEX9tq0iIo3t92a52CZ6qNBQ0Qwe4Ik8B697tn4YCZFJAVYGPJ/ehkUWhU/Q== Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: DM6PR12MB3628.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: e1cac4eb-93d7-4de8-fb91-08d858ba111f X-MS-Exchange-CrossTenant-originalarrivaltime: 14 Sep 2020 14:25:44.5806 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: QlCJQ+2FZ1eSmh3Do7xj1XeIOr15HeaWz4ep5p3zyjvkaS0vRWe1PzrFtPMBi2053PkVnU0tGbLJdiLtCO4Fyg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4233 Subject: Re: [dpdk-dev] [PATCH v2] net/axgbe: enable IEEE 1588 PTP support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" [AMD Official Use Only - Internal Distribution Only] -----Original Message----- From: Sebastian, Selwin Sent: Tuesday, June 9, 2020 8:44 PM To: dev@dpdk.org Cc: Somalapuram, Amaranath Subject: [PATCH v2] net/axgbe: enable IEEE 1588 PTP support From: Selwin Sebastian Add ethdev APIs to support PTP timestamping Signed-off-by: Selwin Sebastian --- drivers/net/axgbe/axgbe_common.h | 8 + drivers/net/axgbe/axgbe_ethdev.c | 336 +++++++++++++++++++++++++ drivers/net/axgbe/axgbe_ethdev.h | 14 ++ drivers/net/axgbe/axgbe_rxtx.c | 8 + drivers/net/axgbe/axgbe_rxtx_vec_sse.c | 8 +- 5 files changed, 373 insertions(+), 1 deletion(-) diff --git a/drivers/net/axgbe/axgbe_common.h b/drivers/net/axgbe/axgbe_com= mon.h index f48117180..e0a0b0fbb 100644 --- a/drivers/net/axgbe/axgbe_common.h +++ b/drivers/net/axgbe/axgbe_common.h @@ -45,6 +45,7 @@ #endif #define AXGBE_HZ250 +#define NSEC_PER_SEC 1000000000L /* DMA register offsets */ #define DMA_MR0x3000 @@ -491,6 +492,8 @@ #define MAC_TSCR_TSEVNTENA_WIDTH1 #define MAC_TSCR_TSINIT_INDEX2 #define MAC_TSCR_TSINIT_WIDTH1 +#define MAC_TSCR_TSUPDT_INDEX3 +#define MAC_TSCR_TSUPDT_WIDTH1 #define MAC_TSCR_TSIPENA_INDEX11 #define MAC_TSCR_TSIPENA_WIDTH1 #define MAC_TSCR_TSIPV4ENA_INDEX13 @@ -505,6 +508,8 @@ #define MAC_TSCR_TXTSSTSM_WIDTH1 #define MAC_TSSR_TXTSC_INDEX15 #define MAC_TSSR_TXTSC_WIDTH1 +#define MAC_STNUR_ADDSUB_INDEX 31 +#define MAC_STNUR_ADDSUB_WIDTH 1 #define MAC_TXSNR_TXTSSTSMIS_INDEX31 #define MAC_TXSNR_TXTSSTSMIS_WIDTH1 #define MAC_VLANHTR_VLHT_INDEX0 @@ -538,6 +543,7 @@ #define MAC_VR_USERVER_INDEX16 #define MAC_VR_USERVER_WIDTH8 + /* MMC register offsets */ #define MMC_CR0x0800 #define MMC_RISR0x0804 @@ -1170,6 +1176,8 @@ #define RX_CONTEXT_DESC3_TSA_WIDTH1 #define RX_CONTEXT_DESC3_TSD_INDEX6 #define RX_CONTEXT_DESC3_TSD_WIDTH1 +#define RX_CONTEXT_DESC3_PMT_INDEX0 +#define RX_CONTEXT_DESC3_PMT_WIDTH4 #define TX_PACKET_ATTRIBUTES_CSUM_ENABLE_INDEX0 #define TX_PACKET_ATTRIBUTES_CSUM_ENABLE_WIDTH1 diff --git a/drivers/net/axgbe/axgbe_ethdev.c b/drivers/net/axgbe/axgbe_eth= dev.c index 867058845..a19bfcb0e 100644 --- a/drivers/net/axgbe/axgbe_ethdev.c +++ b/drivers/net/axgbe/axgbe_ethdev.c @@ -8,6 +8,7 @@ #include "axgbe_common.h" #include "axgbe_phy.h" #include "axgbe_regs.h" +#include "rte_time.h" static int eth_axgbe_dev_init(struct rte_eth_dev *eth_dev); static int et= h_axgbe_dev_uninit(struct rte_eth_dev *eth_dev); @@ -74,6 +75,31 @@ static = void axgbe_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, struct rte_eth_txq_info *qinfo); const uint32_t *axgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev); +static int +axgbe_timesync_enable(struct rte_eth_dev *dev); static int +axgbe_timesync_disable(struct rte_eth_dev *dev); static int +axgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev, +struct timespec *timestamp, uint32_t flags); static int +axgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev, +struct timespec *timestamp); +static int +axgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta); +static int axgbe_timesync_read_time(struct rte_eth_dev *dev, +struct timespec *timestamp); +static int +axgbe_timesync_write_time(struct rte_eth_dev *dev, +const struct timespec *timestamp); +static void +axgbe_set_tstamp_time(struct axgbe_port *pdata, unsigned int sec, +unsigned int nsec); +static void +axgbe_update_tstamp_addend(struct axgbe_port *pdata, +unsigned int addend); + struct axgbe_xstats { char name[RTE_ETH_XSTATS_NAME_SIZE]; int offset; @@ -214,6 +240,14 @@ static const struct eth_dev_ops axgbe_eth_dev_ops =3D = { .dev_supported_ptypes_get =3D axgbe_dev_supported_ptypes_get, .rx_descriptor_status =3D axgbe_dev_rx_descriptor_status, .tx_descriptor_status =3D axgbe_dev_tx_descriptor_status, +.timesync_enable =3D axgbe_timesync_enable, +.timesync_disable =3D axgbe_timesync_disable, +.timesync_read_rx_timestamp =3D axgbe_timesync_read_rx_timestamp, +.timesync_read_tx_timestamp =3D axgbe_timesync_read_tx_timestamp, +.timesync_adjust_time =3D axgbe_timesync_adjust_time, +.timesync_read_time =3D axgbe_timesync_read_time, +.timesync_write_time =3D axgbe_timesync_write_time, + }; static int axgbe_phy_reset(struct axgbe_port *pdata) @@ -1255,6 +1289,308 = @@ axgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev) return NULL; } +static void +axgbe_update_tstamp_time(struct axgbe_port *pdata, +unsigned int sec, unsigned int nsec, int addsub) { +unsigned int count =3D 100; +uint32_t sub_val =3D 0; +uint32_t sub_val_sec =3D 0xFFFFFFFF; +uint32_t sub_val_nsec =3D 0x3B9ACA00; + +if (addsub) { +if (sec) +sub_val =3D sub_val_sec - (sec - 1); +else +sub_val =3D sec; + +AXGMAC_IOWRITE(pdata, MAC_STSUR, sub_val); +sub_val =3D sub_val_nsec - nsec; +AXGMAC_IOWRITE(pdata, MAC_STNUR, sub_val); +AXGMAC_IOWRITE_BITS(pdata, MAC_STNUR, ADDSUB, 1); +} else { +AXGMAC_IOWRITE(pdata, MAC_STSUR, sec); +AXGMAC_IOWRITE_BITS(pdata, MAC_STNUR, ADDSUB, 0); +AXGMAC_IOWRITE(pdata, MAC_STNUR, nsec); +} +AXGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSUPDT, 1); +/* Wait for time update to complete */ +while (--count && AXGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSUPDT)) +rte_delay_ms(1); +} + +static inline uint64_t +div_u64_rem(uint64_t dividend, uint32_t divisor, uint32_t *remainder) { +*remainder =3D dividend % divisor; +return dividend / divisor; +} + +static inline uint64_t +div_u64(uint64_t dividend, uint32_t divisor) { +uint32_t remainder; +return div_u64_rem(dividend, divisor, &remainder); } + +static int +axgbe_adjfreq(struct axgbe_port *pdata, int64_t delta) { +uint64_t adjust; +uint32_t addend, diff; +unsigned int neg_adjust =3D 0; + +if (delta < 0) { +neg_adjust =3D 1; +delta =3D -delta; +} +adjust =3D (uint64_t)pdata->tstamp_addend; +adjust *=3D delta; +diff =3D (uint32_t)div_u64(adjust, 1000000000UL); +addend =3D (neg_adjust) ? pdata->tstamp_addend - diff : +pdata->tstamp_addend + diff; +pdata->tstamp_addend =3D addend; +axgbe_update_tstamp_addend(pdata, addend); +return 0; +} + +static int +axgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta) { +struct axgbe_port *pdata =3D dev->data->dev_private; +struct timespec timestamp_delta; + +axgbe_adjfreq(pdata, delta); +pdata->systime_tc.nsec +=3D delta; + +if (delta < 0) { +delta =3D -delta; +timestamp_delta =3D rte_ns_to_timespec(delta); +axgbe_update_tstamp_time(pdata, timestamp_delta.tv_sec, +timestamp_delta.tv_nsec, 1); +} else { +timestamp_delta =3D rte_ns_to_timespec(delta); +axgbe_update_tstamp_time(pdata, timestamp_delta.tv_sec, +timestamp_delta.tv_nsec, 0); +} +return 0; +} + +static int +axgbe_timesync_read_time(struct rte_eth_dev *dev, +struct timespec *timestamp) +{ +uint64_t nsec; +struct axgbe_port *pdata =3D dev->data->dev_private; + +nsec =3D AXGMAC_IOREAD(pdata, MAC_STSR); +nsec *=3D NSEC_PER_SEC; +nsec +=3D AXGMAC_IOREAD(pdata, MAC_STNR); +*timestamp =3D rte_ns_to_timespec(nsec); +return 0; +} +static int +axgbe_timesync_write_time(struct rte_eth_dev *dev, + const struct timespec *timestamp) { +unsigned int count =3D 100; +struct axgbe_port *pdata =3D dev->data->dev_private; + +AXGMAC_IOWRITE(pdata, MAC_STSUR, timestamp->tv_sec); +AXGMAC_IOWRITE(pdata, MAC_STNUR, timestamp->tv_nsec); +AXGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSUPDT, 1); +/* Wait for time update to complete */ +while (--count && AXGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSUPDT)) +rte_delay_ms(1); +if (!count) +PMD_DRV_LOG(ERR, "Timed out update timestamp\n"); +return 0; +} + +static void +axgbe_update_tstamp_addend(struct axgbe_port *pdata, +uint32_t addend) +{ +unsigned int count =3D 100; + +AXGMAC_IOWRITE(pdata, MAC_TSAR, addend); +AXGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSADDREG, 1); + +/* Wait for addend update to complete */ +while (--count && AXGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSADDREG)) +rte_delay_ms(1); +if (!count) +PMD_DRV_LOG(ERR, "Timed out updating timestamp addend register\n"); } + +static void +axgbe_set_tstamp_time(struct axgbe_port *pdata, unsigned int sec, +unsigned int nsec) +{ +unsigned int count =3D 100; + +/*System Time Sec Update*/ +AXGMAC_IOWRITE(pdata, MAC_STSUR, sec); +/*System Time nanoSec Update*/ +AXGMAC_IOWRITE(pdata, MAC_STNUR, nsec); +/*Initialize Timestamp*/ +AXGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSINIT, 1); + +/* Wait for time update to complete */ +while (--count && AXGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSINIT)) +rte_delay_ms(1); +if (!count) +PMD_DRV_LOG(ERR, "Timed out initializing timestamp\n"); } + +static int +axgbe_timesync_enable(struct rte_eth_dev *dev) { +struct axgbe_port *pdata =3D dev->data->dev_private; +unsigned int mac_tscr =3D 0; +uint64_t dividend; +struct timespec timestamp; +uint64_t nsec; + +/* Set one nano-second accuracy */ +AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCTRLSSR, 1); + +/* Set fine timestamp update */ +AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCFUPDT, 1); + +/* Overwrite earlier timestamps */ +AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TXTSSTSM, 1); + +AXGMAC_IOWRITE(pdata, MAC_TSCR, mac_tscr); + +/* Enabling processing of ptp over eth pkt */ +AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1); +AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1); +/* Enable timestamp for all pkts*/ +AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENALL, 1); + +/* enabling timestamp */ +AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); +AXGMAC_IOWRITE(pdata, MAC_TSCR, mac_tscr); + +/* Exit if timestamping is not enabled */ +if (!AXGMAC_GET_BITS(mac_tscr, MAC_TSCR, TSENA)) { +PMD_DRV_LOG(ERR, "Exiting as timestamp is not enabled\n"); +return 0; +} + +/* Sub-second Increment Value*/ +AXGMAC_IOWRITE_BITS(pdata, MAC_SSIR, SSINC, AXGBE_TSTAMP_SSINC); +/* Sub-nanosecond Increment Value */ +AXGMAC_IOWRITE_BITS(pdata, MAC_SSIR, SNSINC, AXGBE_TSTAMP_SNSINC); + +pdata->ptpclk_rate =3D AXGBE_V2_PTP_CLOCK_FREQ; +dividend =3D 50000000; +dividend <<=3D 32; +pdata->tstamp_addend =3D div_u64(dividend, pdata->ptpclk_rate); + +axgbe_update_tstamp_addend(pdata, pdata->tstamp_addend); +axgbe_set_tstamp_time(pdata, 0, 0); + +/* Initialize the timecounter */ +memset(&pdata->systime_tc, 0, sizeof(struct rte_timecounter)); + +pdata->systime_tc.cc_mask =3D AXGBE_CYCLECOUNTER_MASK; +pdata->systime_tc.cc_shift =3D 0; +pdata->systime_tc.nsec_mask =3D 0; + +PMD_DRV_LOG(DEBUG, "Intializing system time counter with realtime\n"); + +/* Updating the counter once with clock real time */ +clock_gettime(CLOCK_REALTIME, ×tamp); +nsec =3D rte_timespec_to_ns(×tamp); +nsec =3D rte_timecounter_update(&pdata->systime_tc, nsec); +axgbe_set_tstamp_time(pdata, timestamp.tv_sec, timestamp.tv_nsec); +return 0; +} + +static int +axgbe_timesync_disable(struct rte_eth_dev *dev) { +struct axgbe_port *pdata =3D dev->data->dev_private; +unsigned int mac_tscr =3D 0; + +/*disable timestamp for all pkts*/ +AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENALL, 0); +/*disable the addened register*/ +AXGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSADDREG, 0); +/* disable timestamp update */ +AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCFUPDT, 0); +/*disable time stamp*/ +AXGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 0); +return 0; +} + +static int +axgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev, +struct timespec *timestamp, uint32_t flags) { +uint64_t nsec =3D 0; +volatile union axgbe_rx_desc *desc; +uint16_t idx, pmt; +struct axgbe_rx_queue *rxq =3D *dev->data->rx_queues; + +idx =3D AXGBE_GET_DESC_IDX(rxq, rxq->cur); +desc =3D &rxq->desc[idx]; + +while (AXGMAC_GET_BITS_LE(desc->write.desc3, RX_NORMAL_DESC3, OWN)) +rte_delay_ms(1); +if (AXGMAC_GET_BITS_LE(desc->write.desc3, RX_NORMAL_DESC3, CTXT)) { +if (AXGMAC_GET_BITS_LE(desc->write.desc3, RX_CONTEXT_DESC3, TSA) +&& !AXGMAC_GET_BITS_LE(desc->write.desc3, +RX_CONTEXT_DESC3, TSD)) { +pmt =3D AXGMAC_GET_BITS_LE(desc->write.desc3, +RX_CONTEXT_DESC3, PMT); +nsec =3D rte_le_to_cpu_32(desc->write.desc1); +nsec *=3D NSEC_PER_SEC; +nsec +=3D rte_le_to_cpu_32(desc->write.desc0); +if (nsec !=3D 0xffffffffffffffffULL) { +if (pmt =3D=3D 0x01) +*timestamp =3D rte_ns_to_timespec(nsec); +PMD_DRV_LOG(DEBUG, "flags =3D 0x%x nsec =3D %lu\n", +flags, nsec); +} +} +} + +return 0; +} + +static int +axgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev, +struct timespec *timestamp) +{ +uint64_t nsec; +struct axgbe_port *pdata =3D dev->data->dev_private; +unsigned int tx_snr, tx_ssr; + +rte_delay_us(5); +if (pdata->vdata->tx_tstamp_workaround) { +tx_snr =3D AXGMAC_IOREAD(pdata, MAC_TXSNR); +tx_ssr =3D AXGMAC_IOREAD(pdata, MAC_TXSSR); + +} else { +tx_ssr =3D AXGMAC_IOREAD(pdata, MAC_TXSSR); +tx_snr =3D AXGMAC_IOREAD(pdata, MAC_TXSNR); +} +if (AXGMAC_GET_BITS(tx_snr, MAC_TXSNR, TXTSSTSMIS)) { +PMD_DRV_LOG(DEBUG, "Waiting for TXTSSTSMIS\n"); +return 0; +} +nsec =3D tx_ssr; +nsec *=3D NSEC_PER_SEC; +nsec +=3D tx_snr; +PMD_DRV_LOG(DEBUG, "nsec =3D %lu tx_ssr =3D %d tx_snr =3D %d\n", +nsec, tx_ssr, tx_snr); +*timestamp =3D rte_ns_to_timespec(nsec); +return 0; +} + static void axgbe_get_all_hw_features(struct axgbe_port *pdata) { unsigned int mac_hfr0, mac_hfr1, mac_hfr2; diff --git a/drivers/net/axgbe/= axgbe_ethdev.h b/drivers/net/axgbe/axgbe_ethdev.h index f10ec4a40..8a6bbbb22 100644 --- a/drivers/net/axgbe/axgbe_ethdev.h +++ b/drivers/net/axgbe/axgbe_ethdev.h @@ -9,6 +9,7 @@ #include #include #include "axgbe_common.h" +#include "rte_time.h" #define IRQ0xff #define VLAN_HLEN4 @@ -63,6 +64,13 @@ #define AXGBE_V2_DMA_CLOCK_FREQ500000000 #define AXGBE_V2_PTP_CLOCK_FREQ125000000 +/* Timestamp support - values based on 50MHz PTP clock + * 50MHz =3D> 20 nsec + */ +#define AXGBE_TSTAMP_SSINC 20 +#define AXGBE_TSTAMP_SNSINC 0 +#define AXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL + #define AXGMAC_FIFO_MIN_ALLOC2048 #define AXGMAC_FIFO_UNIT256 #define AXGMAC_FIFO_ALIGN(_x) \ @@ -644,6 +652,12 @@ struct axgbe_port { unsigned int hash_table_count; unsigned int uc_hash_mac_addr; unsigned int uc_hash_table[AXGBE_MAC_HASH_TABLE_SIZE]; + +/* For IEEE1588 PTP */ +struct rte_timecounter systime_tc; +struct rte_timecounter tx_tstamp; +unsigned int tstamp_addend; + }; void axgbe_init_function_ptrs_dev(struct axgbe_hw_if *hw_if); diff --git a= /drivers/net/axgbe/axgbe_rxtx.c b/drivers/net/axgbe/axgbe_rxtx.c index 30c4= 67db7..4d4bf59b5 100644 --- a/drivers/net/axgbe/axgbe_rxtx.c +++ b/drivers/net/axgbe/axgbe_rxtx.c @@ -275,6 +275,10 @@ axgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_p= kts, /* Get the RSS hash */ if (AXGMAC_GET_BITS_LE(desc->write.desc3, RX_NORMAL_DESC3, RSV)) mbuf->hash.rss =3D rte_le_to_cpu_32(desc->write.desc1); +/* Indicate if a Context Descriptor is next */ +if (AXGMAC_GET_BITS_LE(desc->write.desc3, RX_NORMAL_DESC3, CDA)) +mbuf->ol_flags |=3D PKT_RX_IEEE1588_PTP +| PKT_RX_IEEE1588_TMST; pkt_len =3D AXGMAC_GET_BITS_LE(desc->write.desc3, RX_NORMAL_DESC3, PL) - rxq->crc_len; /* Mbuf populate */ @@ -722,6 +726,10 @@ static int axgbe_xmit_hw(struct axgbe_tx_queue *txq, /* Total msg length to transmit */ AXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, FL, mbuf->pkt_len); +/* Timestamp enablement check */ +if (mbuf->ol_flags & PKT_TX_IEEE1588_TMST) +AXGMAC_SET_BITS_LE(desc->desc2, TX_NORMAL_DESC2, TTSE, 1); +rte_wmb(); /* Mark it as First and Last Descriptor */ AXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, FD, 1); AXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, LD, 1); diff --git a/driv= ers/net/axgbe/axgbe_rxtx_vec_sse.c b/drivers/net/axgbe/axgbe_rxtx_vec_sse.c index 9be703713..1c962b933 100644 --- a/drivers/net/axgbe/axgbe_rxtx_vec_sse.c +++ b/drivers/net/axgbe/axgbe_rxtx_vec_sse.c @@ -13,6 +13,7 @@ /* Useful to avoid shifting for every descriptor prepration*/ #define TX_= DESC_CTRL_FLAGS 0xb000000000000000 +#define TX_DESC_CTRL_FLAG_TMST 0x40000000 #define TX_FREE_BULK 8 #define TX_FREE_BULK_CHECK (TX_FREE_BULK - 1) @@ -20,8 +21,13 @@ static inline void axgbe_vec_tx(volatile struct axgbe_tx_desc *desc, struct rte_mbuf *mbuf) { +uint64_t tmst_en =3D 0; +/* Timestamp enablement check */ +if (mbuf->ol_flags & PKT_TX_IEEE1588_TMST) +tmst_en =3D TX_DESC_CTRL_FLAG_TMST; __m128i descriptor =3D _mm_set_epi64x((uint64_t)mbuf->pkt_len << 32 | - TX_DESC_CTRL_FLAGS | mbuf->data_len, + TX_DESC_CTRL_FLAGS | mbuf->data_len + | tmst_en, mbuf->buf_iova + mbuf->data_off); _mm_store_si128((__m128i *)desc, descriptor); -- 2.17.1 Acked-by: Amaranath Somalapuram