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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: DM6PR12MB3753.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: a1c04d45-8816-4216-77a3-08daa0525d3c X-MS-Exchange-CrossTenant-originalarrivaltime: 27 Sep 2022 06:34:43.8352 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: ObP7A3LJPv+uv1RjQtNLKaDv7fKHGwQO8Ht+uj1uIosk18rHQU6NEobf9C61bTSf6nWolMjoeG4KMBHcNoKsEw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV2PR12MB5800 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Hi, Honnappa We discussed the barrier here: http://patches.dpdk.org/project/dpdk/patch/20210606164948.35997-1-honnappa.= nagarahalli@arm.com/ (BTW, it is good practice to keep the reference to previous patch versions = below Commit Message of the next ones). This barrier is not about compiler ordering, it is about external HW agent = memory action completions. So, I'm not sure the rte_atomic_thread_fence() is safe for x86 - patch impa= cts x86 as well. With best regards, Slava > -----Original Message----- > From: Honnappa Nagarahalli > Sent: Tuesday, August 30, 2022 23:01 > To: dev@dpdk.org; honnappa.nagarahalli@arm.com; ruifeng.wang@arm.com; Mat= an > Azrad ; Shahaf Shuler ; Slava > Ovsiienko > Cc: nd@arm.com; Matan Azrad ; stable@dpdk.org > Subject: [PATCH v2] net/mlx5: use just sufficient barrier for Arm platfor= ms >=20 > cqe->op_own indicates if the CQE is owned by the NIC. The rest of > the fields in CQE should be read only after op_own is read. On Arm platfo= rms > using "dmb ishld" is sufficient to enforce this. >=20 > Fixes: 88c0733535d6 ("net/mlx5: extend Rx completion with error handling"= ) > Cc: matan@mellanox.com > Cc: stable@dpdk.org >=20 > Signed-off-by: Honnappa Nagarahalli > Reviewed-by: Ruifeng Wang > --- > drivers/common/mlx5/mlx5_common.h | 6 +++++- > 1 file changed, 5 insertions(+), 1 deletion(-) >=20 > diff --git a/drivers/common/mlx5/mlx5_common.h > b/drivers/common/mlx5/mlx5_common.h > index 5028a05b49..ac2e85b15f 100644 > --- a/drivers/common/mlx5/mlx5_common.h > +++ b/drivers/common/mlx5/mlx5_common.h > @@ -195,7 +195,11 @@ check_cqe(volatile struct mlx5_cqe *cqe, const uint1= 6_t > cqes_n, >=20 > if (unlikely((op_owner !=3D (!!(idx))) || (op_code =3D=3D > MLX5_CQE_INVALID))) > return MLX5_CQE_STATUS_HW_OWN; > - rte_io_rmb(); > + /* Prevent speculative reading of other fields in CQE until > + * CQE is valid. > + */ > + rte_atomic_thread_fence(__ATOMIC_ACQUIRE); > + > if (unlikely(op_code =3D=3D MLX5_CQE_RESP_ERR || > op_code =3D=3D MLX5_CQE_REQ_ERR)) > return MLX5_CQE_STATUS_ERR; > -- > 2.17.1