* [dpdk-dev] [PATCH v4 1/1] net/mlx5: support match ICMP identifier fields [not found] <20200930164734.23675-1-lizh@nvidia.co> @ 2020-10-02 8:40 ` Li Zhang 2020-10-04 11:59 ` Ori Kam 2020-10-05 9:18 ` [dpdk-dev] [PATCH v5 " Li Zhang 0 siblings, 2 replies; 14+ messages in thread From: Li Zhang @ 2020-10-02 8:40 UTC (permalink / raw) To: dekelp, orika, viacheslavo, matan; +Cc: dev, thomas, rasland PRM expose fields "Icmp_header_data" in IPv4 ICMP. Update ICMP mask parameter with ICMP identifier and sequence number fields. ICMP sequence number spec with mask, Icmp_header_data low 16 bits are set. ICMP identifier spec with mask, Icmp_header_data high 16 bits are set. Signed-off-by: Li Zhang <lizh@nvidia.com> --- doc/guides/nics/mlx5.rst | 4 ++-- doc/guides/rel_notes/release_20_11.rst | 2 +- drivers/net/mlx5/mlx5_flow.c | 10 ++++++++-- drivers/net/mlx5/mlx5_flow_dv.c | 24 ++++++++++++++++++++++-- 4 files changed, 33 insertions(+), 7 deletions(-) diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst index 211c0c5a6c..576dbe5efd 100644 --- a/doc/guides/nics/mlx5.rst +++ b/doc/guides/nics/mlx5.rst @@ -288,7 +288,7 @@ Limitations - The input buffer, providing the removal size, is not validated. - The buffer size must match the length of the headers to be removed. -- ICMP/ICMP6 code/type matching, IP-in-IP and MPLS flow matching are all +- ICMP(code/type/identifier/sequence number) / ICMP6(code/type) matching, IP-in-IP and MPLS flow matching are all mutually exclusive features which cannot be supported together (see :ref:`mlx5_firmware_config`). @@ -1009,7 +1009,7 @@ Below are some firmware configurations listed. FLEX_PARSER_PROFILE_ENABLE=1 -- enable ICMP/ICMP6 code/type fields matching:: +- enable ICMP(code/type/identifier/sequence number) / ICMP6(code/type) fields matching:: FLEX_PARSER_PROFILE_ENABLE=2 diff --git a/doc/guides/rel_notes/release_20_11.rst b/doc/guides/rel_notes/release_20_11.rst index c6642f5f94..791f133d8f 100644 --- a/doc/guides/rel_notes/release_20_11.rst +++ b/doc/guides/rel_notes/release_20_11.rst @@ -73,7 +73,7 @@ New Features * Added flag action. * Added raw encap/decap actions. * Added VXLAN encap/decap actions. - * Added ICMP and ICMP6 matching items. + * Added ICMP(code/type/identifier/sequence number) and ICMP6(code/type) matching items. * Added option to set port mask for insertion/deletion: ``--portmask=N`` where N represents the hexadecimal bitmask of ports used. diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c index 416505f1c8..3cabfd4627 100644 --- a/drivers/net/mlx5/mlx5_flow.c +++ b/drivers/net/mlx5/mlx5_flow.c @@ -1303,6 +1303,12 @@ mlx5_flow_validate_item_icmp(const struct rte_flow_item *item, struct rte_flow_error *error) { const struct rte_flow_item_icmp *mask = item->mask; + const struct rte_flow_item_icmp nic_mask = { + .hdr.icmp_type = 0xff, + .hdr.icmp_code = 0xff, + .hdr.icmp_ident = RTE_BE16(0xffff), + .hdr.icmp_seq_nb = RTE_BE16(0xffff), + }; const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 : MLX5_FLOW_LAYER_OUTER_L3_IPV4; @@ -1325,10 +1331,10 @@ mlx5_flow_validate_item_icmp(const struct rte_flow_item *item, RTE_FLOW_ERROR_TYPE_ITEM, item, "multiple L4 layers not supported"); if (!mask) - mask = &rte_flow_item_icmp_mask; + mask = &nic_mask; ret = mlx5_flow_item_acceptable (item, (const uint8_t *)mask, - (const uint8_t *)&rte_flow_item_icmp_mask, + (const uint8_t *)&nic_mask, sizeof(struct rte_flow_item_icmp), error); if (ret < 0) return ret; diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index 3819cdb266..a0b78934fd 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -7378,6 +7378,14 @@ flow_dv_translate_item_icmp(void *matcher, void *key, { const struct rte_flow_item_icmp *icmp_m = item->mask; const struct rte_flow_item_icmp *icmp_v = item->spec; + const struct rte_flow_item_icmp nic_mask = { + .hdr.icmp_type = 0xff, + .hdr.icmp_code = 0xff, + .hdr.icmp_ident = RTE_BE16(0xffff), + .hdr.icmp_seq_nb = RTE_BE16(0xffff), + }; + uint32_t icmp_header_data_m = 0; + uint32_t icmp_header_data_v = 0; void *headers_m; void *headers_v; void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher, @@ -7396,8 +7404,14 @@ flow_dv_translate_item_icmp(void *matcher, void *key, MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP); if (!icmp_v) return; - if (!icmp_m) - icmp_m = &rte_flow_item_icmp_mask; + if (!icmp_m) { + icmp_m = &nic_mask; + icmp_header_data_m = UINT32_MAX; + } else { + icmp_header_data_m = rte_be_to_cpu_16(icmp_m->hdr.icmp_seq_nb); + icmp_header_data_m |= + rte_be_to_cpu_16(icmp_m->hdr.icmp_ident) << 16; + } /* * Force flow only to match the non-fragmented IPv4 ICMP packets. * If only the protocol is specified, no need to match the frag. @@ -7412,6 +7426,12 @@ flow_dv_translate_item_icmp(void *matcher, void *key, icmp_m->hdr.icmp_code); MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code, icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code); + icmp_header_data_v = rte_be_to_cpu_16(icmp_v->hdr.icmp_seq_nb); + icmp_header_data_v |= rte_be_to_cpu_16(icmp_v->hdr.icmp_ident) << 16; + MLX5_SET(fte_match_set_misc3, misc3_m, icmp_header_data, + icmp_header_data_m); + MLX5_SET(fte_match_set_misc3, misc3_v, icmp_header_data, + icmp_header_data_v & icmp_header_data_m); } /** -- 2.21.0 ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [dpdk-dev] [PATCH v4 1/1] net/mlx5: support match ICMP identifier fields 2020-10-02 8:40 ` [dpdk-dev] [PATCH v4 1/1] net/mlx5: support match ICMP identifier fields Li Zhang @ 2020-10-04 11:59 ` Ori Kam 2020-10-05 9:20 ` Li Zhang 2020-10-05 9:18 ` [dpdk-dev] [PATCH v5 " Li Zhang 1 sibling, 1 reply; 14+ messages in thread From: Ori Kam @ 2020-10-04 11:59 UTC (permalink / raw) To: Li Zhang, Dekel Peled, Slava Ovsiienko, Matan Azrad Cc: dev, NBU-Contact-Thomas Monjalon, Raslan Darawsheh Hi Li PSB Best, Ori > -----Original Message----- > From: dev <dev-bounces@dpdk.org> On Behalf Of Li Zhang > Sent: Friday, October 2, 2020 11:41 AM > Subject: [dpdk-dev] [PATCH v4 1/1] net/mlx5: support match ICMP identifier > fields > > PRM expose fields "Icmp_header_data" in IPv4 ICMP. > Update ICMP mask parameter with ICMP identifier and sequence number > fields. > ICMP sequence number spec with mask, Icmp_header_data low 16 bits are set. > ICMP identifier spec with mask, Icmp_header_data high 16 bits are set. > > Signed-off-by: Li Zhang <lizh@nvidia.com> > --- > doc/guides/nics/mlx5.rst | 4 ++-- > doc/guides/rel_notes/release_20_11.rst | 2 +- > drivers/net/mlx5/mlx5_flow.c | 10 ++++++++-- > drivers/net/mlx5/mlx5_flow_dv.c | 24 ++++++++++++++++++++++-- > 4 files changed, 33 insertions(+), 7 deletions(-) > > diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst > index 211c0c5a6c..576dbe5efd 100644 > --- a/doc/guides/nics/mlx5.rst > +++ b/doc/guides/nics/mlx5.rst > @@ -288,7 +288,7 @@ Limitations > - The input buffer, providing the removal size, is not validated. > - The buffer size must match the length of the headers to be removed. > > -- ICMP/ICMP6 code/type matching, IP-in-IP and MPLS flow matching are all > +- ICMP(code/type/identifier/sequence number) / ICMP6(code/type) matching, > IP-in-IP and MPLS flow matching are all > mutually exclusive features which cannot be supported together > (see :ref:`mlx5_firmware_config`). > > @@ -1009,7 +1009,7 @@ Below are some firmware configurations listed. > > FLEX_PARSER_PROFILE_ENABLE=1 > > -- enable ICMP/ICMP6 code/type fields matching:: > +- enable ICMP(code/type/identifier/sequence number) / ICMP6(code/type) > fields matching:: > > FLEX_PARSER_PROFILE_ENABLE=2 > > diff --git a/doc/guides/rel_notes/release_20_11.rst > b/doc/guides/rel_notes/release_20_11.rst > index c6642f5f94..791f133d8f 100644 > --- a/doc/guides/rel_notes/release_20_11.rst > +++ b/doc/guides/rel_notes/release_20_11.rst > @@ -73,7 +73,7 @@ New Features > * Added flag action. > * Added raw encap/decap actions. > * Added VXLAN encap/decap actions. > - * Added ICMP and ICMP6 matching items. > + * Added ICMP(code/type/identifier/sequence number) and > ICMP6(code/type) matching items. > * Added option to set port mask for insertion/deletion: > ``--portmask=N`` > where N represents the hexadecimal bitmask of ports used. > diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c > index 416505f1c8..3cabfd4627 100644 > --- a/drivers/net/mlx5/mlx5_flow.c > +++ b/drivers/net/mlx5/mlx5_flow.c > @@ -1303,6 +1303,12 @@ mlx5_flow_validate_item_icmp(const struct > rte_flow_item *item, > struct rte_flow_error *error) > { > const struct rte_flow_item_icmp *mask = item->mask; > + const struct rte_flow_item_icmp nic_mask = { > + .hdr.icmp_type = 0xff, > + .hdr.icmp_code = 0xff, > + .hdr.icmp_ident = RTE_BE16(0xffff), > + .hdr.icmp_seq_nb = RTE_BE16(0xffff), > + }; > const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); > const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 : > MLX5_FLOW_LAYER_OUTER_L3_IPV4; > @@ -1325,10 +1331,10 @@ mlx5_flow_validate_item_icmp(const struct > rte_flow_item *item, > RTE_FLOW_ERROR_TYPE_ITEM, > item, > "multiple L4 layers not supported"); > if (!mask) > - mask = &rte_flow_item_icmp_mask; > + mask = &nic_mask; > ret = mlx5_flow_item_acceptable > (item, (const uint8_t *)mask, > - (const uint8_t *)&rte_flow_item_icmp_mask, > + (const uint8_t *)&nic_mask, > sizeof(struct rte_flow_item_icmp), error); > if (ret < 0) > return ret; > diff --git a/drivers/net/mlx5/mlx5_flow_dv.c > b/drivers/net/mlx5/mlx5_flow_dv.c > index 3819cdb266..a0b78934fd 100644 > --- a/drivers/net/mlx5/mlx5_flow_dv.c > +++ b/drivers/net/mlx5/mlx5_flow_dv.c > @@ -7378,6 +7378,14 @@ flow_dv_translate_item_icmp(void *matcher, void > *key, > { > const struct rte_flow_item_icmp *icmp_m = item->mask; > const struct rte_flow_item_icmp *icmp_v = item->spec; > + const struct rte_flow_item_icmp nic_mask = { > + .hdr.icmp_type = 0xff, > + .hdr.icmp_code = 0xff, > + .hdr.icmp_ident = RTE_BE16(0xffff), > + .hdr.icmp_seq_nb = RTE_BE16(0xffff), > + }; This is incorrect, like before, you are changing existing app behavior. Think about it this way, until now the app didn't place any mask so he just matched on the rte_default now with our new version all the matching will fail. Since you are adding more must fields. > + uint32_t icmp_header_data_m = 0; > + uint32_t icmp_header_data_v = 0; > void *headers_m; > void *headers_v; > void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher, > @@ -7396,8 +7404,14 @@ flow_dv_translate_item_icmp(void *matcher, void > *key, > MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, > IPPROTO_ICMP); > if (!icmp_v) > return; > - if (!icmp_m) > - icmp_m = &rte_flow_item_icmp_mask; > + if (!icmp_m) { > + icmp_m = &nic_mask; > + icmp_header_data_m = UINT32_MAX; Please see comment above. > + } else { > + icmp_header_data_m = rte_be_to_cpu_16(icmp_m- > >hdr.icmp_seq_nb); > + icmp_header_data_m |= > + rte_be_to_cpu_16(icmp_m->hdr.icmp_ident) << 16; > + } > /* > * Force flow only to match the non-fragmented IPv4 ICMP packets. > * If only the protocol is specified, no need to match the frag. > @@ -7412,6 +7426,12 @@ flow_dv_translate_item_icmp(void *matcher, void > *key, > icmp_m->hdr.icmp_code); > MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code, > icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code); > + icmp_header_data_v = rte_be_to_cpu_16(icmp_v->hdr.icmp_seq_nb); > + icmp_header_data_v |= rte_be_to_cpu_16(icmp_v->hdr.icmp_ident) > << 16; > + MLX5_SET(fte_match_set_misc3, misc3_m, icmp_header_data, > + icmp_header_data_m); > + MLX5_SET(fte_match_set_misc3, misc3_v, icmp_header_data, > + icmp_header_data_v & icmp_header_data_m); > } > > /** > -- > 2.21.0 ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [dpdk-dev] [PATCH v4 1/1] net/mlx5: support match ICMP identifier fields 2020-10-04 11:59 ` Ori Kam @ 2020-10-05 9:20 ` Li Zhang 2020-10-05 9:41 ` Li Zhang 0 siblings, 1 reply; 14+ messages in thread From: Li Zhang @ 2020-10-05 9:20 UTC (permalink / raw) To: Ori Kam, Dekel Peled, Slava Ovsiienko, Matan Azrad Cc: dev, NBU-Contact-Thomas Monjalon, Raslan Darawsheh Hi Qri, Thanks for your comments. I will update it in V5 patch. Please help review it to make sure I got your point. Regards, Li Zhang > -----Original Message----- > From: Ori Kam <orika@nvidia.com> > Sent: Sunday, October 4, 2020 7:59 PM > To: Li Zhang <lizh@nvidia.com>; Dekel Peled <dekelp@nvidia.com>; Slava > Ovsiienko <viacheslavo@nvidia.com>; Matan Azrad <matan@nvidia.com> > Cc: dev@dpdk.org; NBU-Contact-Thomas Monjalon > <thomas@monjalon.net>; Raslan Darawsheh <rasland@nvidia.com> > Subject: RE: [dpdk-dev] [PATCH v4 1/1] net/mlx5: support match ICMP > identifier fields > > Hi Li > > PSB > > Best, > Ori > > -----Original Message----- > > From: dev <dev-bounces@dpdk.org> On Behalf Of Li Zhang > > Sent: Friday, October 2, 2020 11:41 AM > > Subject: [dpdk-dev] [PATCH v4 1/1] net/mlx5: support match ICMP > > identifier fields > > > > PRM expose fields "Icmp_header_data" in IPv4 ICMP. > > Update ICMP mask parameter with ICMP identifier and sequence number > > fields. > > ICMP sequence number spec with mask, Icmp_header_data low 16 bits are > set. > > ICMP identifier spec with mask, Icmp_header_data high 16 bits are set. > > > > Signed-off-by: Li Zhang <lizh@nvidia.com> > > --- > > doc/guides/nics/mlx5.rst | 4 ++-- > > doc/guides/rel_notes/release_20_11.rst | 2 +- > > drivers/net/mlx5/mlx5_flow.c | 10 ++++++++-- > > drivers/net/mlx5/mlx5_flow_dv.c | 24 ++++++++++++++++++++++-- > > 4 files changed, 33 insertions(+), 7 deletions(-) > > > > diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst index > > 211c0c5a6c..576dbe5efd 100644 > > --- a/doc/guides/nics/mlx5.rst > > +++ b/doc/guides/nics/mlx5.rst > > @@ -288,7 +288,7 @@ Limitations > > - The input buffer, providing the removal size, is not validated. > > - The buffer size must match the length of the headers to be removed. > > > > -- ICMP/ICMP6 code/type matching, IP-in-IP and MPLS flow matching are > > all > > +- ICMP(code/type/identifier/sequence number) / ICMP6(code/type) > > +matching, > > IP-in-IP and MPLS flow matching are all > > mutually exclusive features which cannot be supported together > > (see :ref:`mlx5_firmware_config`). > > > > @@ -1009,7 +1009,7 @@ Below are some firmware configurations listed. > > > > FLEX_PARSER_PROFILE_ENABLE=1 > > > > -- enable ICMP/ICMP6 code/type fields matching:: > > +- enable ICMP(code/type/identifier/sequence number) / > > +ICMP6(code/type) > > fields matching:: > > > > FLEX_PARSER_PROFILE_ENABLE=2 > > > > diff --git a/doc/guides/rel_notes/release_20_11.rst > > b/doc/guides/rel_notes/release_20_11.rst > > index c6642f5f94..791f133d8f 100644 > > --- a/doc/guides/rel_notes/release_20_11.rst > > +++ b/doc/guides/rel_notes/release_20_11.rst > > @@ -73,7 +73,7 @@ New Features > > * Added flag action. > > * Added raw encap/decap actions. > > * Added VXLAN encap/decap actions. > > - * Added ICMP and ICMP6 matching items. > > + * Added ICMP(code/type/identifier/sequence number) and > > ICMP6(code/type) matching items. > > * Added option to set port mask for insertion/deletion: > > ``--portmask=N`` > > where N represents the hexadecimal bitmask of ports used. > > diff --git a/drivers/net/mlx5/mlx5_flow.c > > b/drivers/net/mlx5/mlx5_flow.c index 416505f1c8..3cabfd4627 100644 > > --- a/drivers/net/mlx5/mlx5_flow.c > > +++ b/drivers/net/mlx5/mlx5_flow.c > > @@ -1303,6 +1303,12 @@ mlx5_flow_validate_item_icmp(const struct > > rte_flow_item *item, > > struct rte_flow_error *error) { > > const struct rte_flow_item_icmp *mask = item->mask; > > + const struct rte_flow_item_icmp nic_mask = { > > + .hdr.icmp_type = 0xff, > > + .hdr.icmp_code = 0xff, > > + .hdr.icmp_ident = RTE_BE16(0xffff), > > + .hdr.icmp_seq_nb = RTE_BE16(0xffff), > > + }; > > const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); > > const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 : > > MLX5_FLOW_LAYER_OUTER_L3_IPV4; > @@ -1325,10 +1331,10 @@ > > mlx5_flow_validate_item_icmp(const struct rte_flow_item *item, > > RTE_FLOW_ERROR_TYPE_ITEM, > > item, > > "multiple L4 layers not supported"); > > if (!mask) > > - mask = &rte_flow_item_icmp_mask; > > + mask = &nic_mask; > > ret = mlx5_flow_item_acceptable > > (item, (const uint8_t *)mask, > > - (const uint8_t *)&rte_flow_item_icmp_mask, > > + (const uint8_t *)&nic_mask, > > sizeof(struct rte_flow_item_icmp), error); > > if (ret < 0) > > return ret; > > diff --git a/drivers/net/mlx5/mlx5_flow_dv.c > > b/drivers/net/mlx5/mlx5_flow_dv.c index 3819cdb266..a0b78934fd 100644 > > --- a/drivers/net/mlx5/mlx5_flow_dv.c > > +++ b/drivers/net/mlx5/mlx5_flow_dv.c > > @@ -7378,6 +7378,14 @@ flow_dv_translate_item_icmp(void *matcher, > void > > *key, { > > const struct rte_flow_item_icmp *icmp_m = item->mask; > > const struct rte_flow_item_icmp *icmp_v = item->spec; > > + const struct rte_flow_item_icmp nic_mask = { > > + .hdr.icmp_type = 0xff, > > + .hdr.icmp_code = 0xff, > > + .hdr.icmp_ident = RTE_BE16(0xffff), > > + .hdr.icmp_seq_nb = RTE_BE16(0xffff), > > + }; > > This is incorrect, like before, you are changing existing app behavior. > Think about it this way, until now the app didn't place any mask so he just > matched on the rte_default now with our new version all the matching will > fail. Since you are adding more must fields. > > > + uint32_t icmp_header_data_m = 0; > > + uint32_t icmp_header_data_v = 0; > > void *headers_m; > > void *headers_v; > > void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher, @@ - > 7396,8 > > +7404,14 @@ flow_dv_translate_item_icmp(void *matcher, void *key, > > MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, > > IPPROTO_ICMP); > > if (!icmp_v) > > return; > > - if (!icmp_m) > > - icmp_m = &rte_flow_item_icmp_mask; > > + if (!icmp_m) { > > + icmp_m = &nic_mask; > > + icmp_header_data_m = UINT32_MAX; > > Please see comment above. > > > + } else { > > + icmp_header_data_m = rte_be_to_cpu_16(icmp_m- > > >hdr.icmp_seq_nb); > > + icmp_header_data_m |= > > + rte_be_to_cpu_16(icmp_m->hdr.icmp_ident) << 16; > > + } > > /* > > * Force flow only to match the non-fragmented IPv4 ICMP packets. > > * If only the protocol is specified, no need to match the frag. > > @@ -7412,6 +7426,12 @@ flow_dv_translate_item_icmp(void *matcher, > void > > *key, > > icmp_m->hdr.icmp_code); > > MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code, > > icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code); > > + icmp_header_data_v = rte_be_to_cpu_16(icmp_v- > >hdr.icmp_seq_nb); > > + icmp_header_data_v |= rte_be_to_cpu_16(icmp_v->hdr.icmp_ident) > > << 16; > > + MLX5_SET(fte_match_set_misc3, misc3_m, icmp_header_data, > > + icmp_header_data_m); > > + MLX5_SET(fte_match_set_misc3, misc3_v, icmp_header_data, > > + icmp_header_data_v & icmp_header_data_m); > > } > > > > /** > > -- > > 2.21.0 ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [dpdk-dev] [PATCH v4 1/1] net/mlx5: support match ICMP identifier fields 2020-10-05 9:20 ` Li Zhang @ 2020-10-05 9:41 ` Li Zhang 0 siblings, 0 replies; 14+ messages in thread From: Li Zhang @ 2020-10-05 9:41 UTC (permalink / raw) To: Ori Kam, Dekel Peled, Slava Ovsiienko, Matan Azrad Cc: dev, NBU-Contact-Thomas Monjalon, Raslan Darawsheh Hi Qri, Please help review the new patch V6 https://patchwork.dpdk.org/patch/79613/ Regards, Li Zhang > -----Original Message----- > From: Li Zhang > Sent: Monday, October 5, 2020 5:20 PM > To: Ori Kam <orika@nvidia.com>; Dekel Peled <dekelp@nvidia.com>; Slava > Ovsiienko <viacheslavo@nvidia.com>; Matan Azrad <matan@nvidia.com> > Cc: dev@dpdk.org; NBU-Contact-Thomas Monjalon > <thomas@monjalon.net>; Raslan Darawsheh <rasland@nvidia.com> > Subject: RE: [dpdk-dev] [PATCH v4 1/1] net/mlx5: support match ICMP > identifier fields > > Hi Qri, > > Thanks for your comments. > I will update it in V5 patch. > Please help review it to make sure I got your point. > > Regards, > Li Zhang > > > -----Original Message----- > > From: Ori Kam <orika@nvidia.com> > > Sent: Sunday, October 4, 2020 7:59 PM > > To: Li Zhang <lizh@nvidia.com>; Dekel Peled <dekelp@nvidia.com>; Slava > > Ovsiienko <viacheslavo@nvidia.com>; Matan Azrad <matan@nvidia.com> > > Cc: dev@dpdk.org; NBU-Contact-Thomas Monjalon > <thomas@monjalon.net>; > > Raslan Darawsheh <rasland@nvidia.com> > > Subject: RE: [dpdk-dev] [PATCH v4 1/1] net/mlx5: support match ICMP > > identifier fields > > > > Hi Li > > > > PSB > > > > Best, > > Ori > > > -----Original Message----- > > > From: dev <dev-bounces@dpdk.org> On Behalf Of Li Zhang > > > Sent: Friday, October 2, 2020 11:41 AM > > > Subject: [dpdk-dev] [PATCH v4 1/1] net/mlx5: support match ICMP > > > identifier fields > > > > > > PRM expose fields "Icmp_header_data" in IPv4 ICMP. > > > Update ICMP mask parameter with ICMP identifier and sequence number > > > fields. > > > ICMP sequence number spec with mask, Icmp_header_data low 16 bits > > > are > > set. > > > ICMP identifier spec with mask, Icmp_header_data high 16 bits are set. > > > > > > Signed-off-by: Li Zhang <lizh@nvidia.com> > > > --- > > > doc/guides/nics/mlx5.rst | 4 ++-- > > > doc/guides/rel_notes/release_20_11.rst | 2 +- > > > drivers/net/mlx5/mlx5_flow.c | 10 ++++++++-- > > > drivers/net/mlx5/mlx5_flow_dv.c | 24 ++++++++++++++++++++++-- > > > 4 files changed, 33 insertions(+), 7 deletions(-) > > > > > > diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst > > > index 211c0c5a6c..576dbe5efd 100644 > > > --- a/doc/guides/nics/mlx5.rst > > > +++ b/doc/guides/nics/mlx5.rst > > > @@ -288,7 +288,7 @@ Limitations > > > - The input buffer, providing the removal size, is not validated. > > > - The buffer size must match the length of the headers to be removed. > > > > > > -- ICMP/ICMP6 code/type matching, IP-in-IP and MPLS flow matching > > > are all > > > +- ICMP(code/type/identifier/sequence number) / ICMP6(code/type) > > > +matching, > > > IP-in-IP and MPLS flow matching are all > > > mutually exclusive features which cannot be supported together > > > (see :ref:`mlx5_firmware_config`). > > > > > > @@ -1009,7 +1009,7 @@ Below are some firmware configurations listed. > > > > > > FLEX_PARSER_PROFILE_ENABLE=1 > > > > > > -- enable ICMP/ICMP6 code/type fields matching:: > > > +- enable ICMP(code/type/identifier/sequence number) / > > > +ICMP6(code/type) > > > fields matching:: > > > > > > FLEX_PARSER_PROFILE_ENABLE=2 > > > > > > diff --git a/doc/guides/rel_notes/release_20_11.rst > > > b/doc/guides/rel_notes/release_20_11.rst > > > index c6642f5f94..791f133d8f 100644 > > > --- a/doc/guides/rel_notes/release_20_11.rst > > > +++ b/doc/guides/rel_notes/release_20_11.rst > > > @@ -73,7 +73,7 @@ New Features > > > * Added flag action. > > > * Added raw encap/decap actions. > > > * Added VXLAN encap/decap actions. > > > - * Added ICMP and ICMP6 matching items. > > > + * Added ICMP(code/type/identifier/sequence number) and > > > ICMP6(code/type) matching items. > > > * Added option to set port mask for insertion/deletion: > > > ``--portmask=N`` > > > where N represents the hexadecimal bitmask of ports used. > > > diff --git a/drivers/net/mlx5/mlx5_flow.c > > > b/drivers/net/mlx5/mlx5_flow.c index 416505f1c8..3cabfd4627 100644 > > > --- a/drivers/net/mlx5/mlx5_flow.c > > > +++ b/drivers/net/mlx5/mlx5_flow.c > > > @@ -1303,6 +1303,12 @@ mlx5_flow_validate_item_icmp(const struct > > > rte_flow_item *item, > > > struct rte_flow_error *error) { > > > const struct rte_flow_item_icmp *mask = item->mask; > > > + const struct rte_flow_item_icmp nic_mask = { > > > + .hdr.icmp_type = 0xff, > > > + .hdr.icmp_code = 0xff, > > > + .hdr.icmp_ident = RTE_BE16(0xffff), > > > + .hdr.icmp_seq_nb = RTE_BE16(0xffff), > > > + }; > > > const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); > > > const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 : > > > MLX5_FLOW_LAYER_OUTER_L3_IPV4; > > @@ -1325,10 +1331,10 @@ > > > mlx5_flow_validate_item_icmp(const struct rte_flow_item *item, > > > RTE_FLOW_ERROR_TYPE_ITEM, > > > item, > > > "multiple L4 layers not supported"); > > > if (!mask) > > > - mask = &rte_flow_item_icmp_mask; > > > + mask = &nic_mask; > > > ret = mlx5_flow_item_acceptable > > > (item, (const uint8_t *)mask, > > > - (const uint8_t *)&rte_flow_item_icmp_mask, > > > + (const uint8_t *)&nic_mask, > > > sizeof(struct rte_flow_item_icmp), error); > > > if (ret < 0) > > > return ret; > > > diff --git a/drivers/net/mlx5/mlx5_flow_dv.c > > > b/drivers/net/mlx5/mlx5_flow_dv.c index 3819cdb266..a0b78934fd > > > 100644 > > > --- a/drivers/net/mlx5/mlx5_flow_dv.c > > > +++ b/drivers/net/mlx5/mlx5_flow_dv.c > > > @@ -7378,6 +7378,14 @@ flow_dv_translate_item_icmp(void *matcher, > > void > > > *key, { > > > const struct rte_flow_item_icmp *icmp_m = item->mask; > > > const struct rte_flow_item_icmp *icmp_v = item->spec; > > > + const struct rte_flow_item_icmp nic_mask = { > > > + .hdr.icmp_type = 0xff, > > > + .hdr.icmp_code = 0xff, > > > + .hdr.icmp_ident = RTE_BE16(0xffff), > > > + .hdr.icmp_seq_nb = RTE_BE16(0xffff), > > > + }; > > > > This is incorrect, like before, you are changing existing app behavior. > > Think about it this way, until now the app didn't place any mask so he > > just matched on the rte_default now with our new version all the > > matching will fail. Since you are adding more must fields. > > > > > + uint32_t icmp_header_data_m = 0; > > > + uint32_t icmp_header_data_v = 0; > > > void *headers_m; > > > void *headers_v; > > > void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher, @@ - > > 7396,8 > > > +7404,14 @@ flow_dv_translate_item_icmp(void *matcher, void *key, > > > MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, > > > IPPROTO_ICMP); > > > if (!icmp_v) > > > return; > > > - if (!icmp_m) > > > - icmp_m = &rte_flow_item_icmp_mask; > > > + if (!icmp_m) { > > > + icmp_m = &nic_mask; > > > + icmp_header_data_m = UINT32_MAX; > > > > Please see comment above. > > > > > + } else { > > > + icmp_header_data_m = rte_be_to_cpu_16(icmp_m- > > > >hdr.icmp_seq_nb); > > > + icmp_header_data_m |= > > > + rte_be_to_cpu_16(icmp_m->hdr.icmp_ident) << 16; > > > + } > > > /* > > > * Force flow only to match the non-fragmented IPv4 ICMP packets. > > > * If only the protocol is specified, no need to match the frag. > > > @@ -7412,6 +7426,12 @@ flow_dv_translate_item_icmp(void *matcher, > > void > > > *key, > > > icmp_m->hdr.icmp_code); > > > MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code, > > > icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code); > > > + icmp_header_data_v = rte_be_to_cpu_16(icmp_v- > > >hdr.icmp_seq_nb); > > > + icmp_header_data_v |= rte_be_to_cpu_16(icmp_v->hdr.icmp_ident) > > > << 16; > > > + MLX5_SET(fte_match_set_misc3, misc3_m, icmp_header_data, > > > + icmp_header_data_m); > > > + MLX5_SET(fte_match_set_misc3, misc3_v, icmp_header_data, > > > + icmp_header_data_v & icmp_header_data_m); > > > } > > > > > > /** > > > -- > > > 2.21.0 ^ permalink raw reply [flat|nested] 14+ messages in thread
* [dpdk-dev] [PATCH v5 1/1] net/mlx5: support match ICMP identifier fields 2020-10-02 8:40 ` [dpdk-dev] [PATCH v4 1/1] net/mlx5: support match ICMP identifier fields Li Zhang 2020-10-04 11:59 ` Ori Kam @ 2020-10-05 9:18 ` Li Zhang 2020-10-05 9:31 ` [dpdk-dev] [PATCH v6 " Li Zhang 1 sibling, 1 reply; 14+ messages in thread From: Li Zhang @ 2020-10-05 9:18 UTC (permalink / raw) To: dekelp, orika, viacheslavo, matan; +Cc: dev, thomas, rasland PRM expose fields "Icmp_header_data" in IPv4 ICMP. Update ICMP mask parameter with ICMP identifier and sequence number fields. ICMP sequence number spec with mask, Icmp_header_data low 16 bits are set. ICMP identifier spec with mask, Icmp_header_data high 16 bits are set. Signed-off-by: Li Zhang <lizh@nvidia.com> --- doc/guides/nics/mlx5.rst | 4 ++-- doc/guides/rel_notes/release_20_11.rst | 2 +- drivers/net/mlx5/mlx5_flow.c | 10 ++++++++-- drivers/net/mlx5/mlx5_flow_dv.c | 12 ++++++++++++ 4 files changed, 23 insertions(+), 5 deletions(-) diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst index 211c0c5a6c..576dbe5efd 100644 --- a/doc/guides/nics/mlx5.rst +++ b/doc/guides/nics/mlx5.rst @@ -288,7 +288,7 @@ Limitations - The input buffer, providing the removal size, is not validated. - The buffer size must match the length of the headers to be removed. -- ICMP/ICMP6 code/type matching, IP-in-IP and MPLS flow matching are all +- ICMP(code/type/identifier/sequence number) / ICMP6(code/type) matching, IP-in-IP and MPLS flow matching are all mutually exclusive features which cannot be supported together (see :ref:`mlx5_firmware_config`). @@ -1009,7 +1009,7 @@ Below are some firmware configurations listed. FLEX_PARSER_PROFILE_ENABLE=1 -- enable ICMP/ICMP6 code/type fields matching:: +- enable ICMP(code/type/identifier/sequence number) / ICMP6(code/type) fields matching:: FLEX_PARSER_PROFILE_ENABLE=2 diff --git a/doc/guides/rel_notes/release_20_11.rst b/doc/guides/rel_notes/release_20_11.rst index c6642f5f94..791f133d8f 100644 --- a/doc/guides/rel_notes/release_20_11.rst +++ b/doc/guides/rel_notes/release_20_11.rst @@ -73,7 +73,7 @@ New Features * Added flag action. * Added raw encap/decap actions. * Added VXLAN encap/decap actions. - * Added ICMP and ICMP6 matching items. + * Added ICMP(code/type/identifier/sequence number) and ICMP6(code/type) matching items. * Added option to set port mask for insertion/deletion: ``--portmask=N`` where N represents the hexadecimal bitmask of ports used. diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c index 416505f1c8..3cabfd4627 100644 --- a/drivers/net/mlx5/mlx5_flow.c +++ b/drivers/net/mlx5/mlx5_flow.c @@ -1303,6 +1303,12 @@ mlx5_flow_validate_item_icmp(const struct rte_flow_item *item, struct rte_flow_error *error) { const struct rte_flow_item_icmp *mask = item->mask; + const struct rte_flow_item_icmp nic_mask = { + .hdr.icmp_type = 0xff, + .hdr.icmp_code = 0xff, + .hdr.icmp_ident = RTE_BE16(0xffff), + .hdr.icmp_seq_nb = RTE_BE16(0xffff), + }; const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 : MLX5_FLOW_LAYER_OUTER_L3_IPV4; @@ -1325,10 +1331,10 @@ mlx5_flow_validate_item_icmp(const struct rte_flow_item *item, RTE_FLOW_ERROR_TYPE_ITEM, item, "multiple L4 layers not supported"); if (!mask) - mask = &rte_flow_item_icmp_mask; + mask = &nic_mask; ret = mlx5_flow_item_acceptable (item, (const uint8_t *)mask, - (const uint8_t *)&rte_flow_item_icmp_mask, + (const uint8_t *)&nic_mask, sizeof(struct rte_flow_item_icmp), error); if (ret < 0) return ret; diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index 3819cdb266..6c7180e53d 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -7378,6 +7378,8 @@ flow_dv_translate_item_icmp(void *matcher, void *key, { const struct rte_flow_item_icmp *icmp_m = item->mask; const struct rte_flow_item_icmp *icmp_v = item->spec; + uint32_t icmp_header_data_m = 0; + uint32_t icmp_header_data_v = 0; void *headers_m; void *headers_v; void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher, @@ -7412,6 +7414,16 @@ flow_dv_translate_item_icmp(void *matcher, void *key, icmp_m->hdr.icmp_code); MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code, icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code); + icmp_header_data_m = rte_be_to_cpu_16(icmp_m->hdr.icmp_seq_nb); + icmp_header_data_m |= rte_be_to_cpu_16(icmp_m->hdr.icmp_ident) << 16; + if (icmp_header_data_m) { + icmp_header_data_v = rte_be_to_cpu_16(icmp_v->hdr.icmp_seq_nb); + icmp_header_data_v |= rte_be_to_cpu_16(icmp_v->hdr.icmp_ident) << 16; + MLX5_SET(fte_match_set_misc3, misc3_m, icmp_header_data, + icmp_header_data_m); + MLX5_SET(fte_match_set_misc3, misc3_v, icmp_header_data, + icmp_header_data_v & icmp_header_data_m); + } } /** -- 2.21.0 ^ permalink raw reply [flat|nested] 14+ messages in thread
* [dpdk-dev] [PATCH v6 1/1] net/mlx5: support match ICMP identifier fields 2020-10-05 9:18 ` [dpdk-dev] [PATCH v5 " Li Zhang @ 2020-10-05 9:31 ` Li Zhang 2020-10-05 10:33 ` Ori Kam 2020-10-09 6:01 ` [dpdk-dev] [PATCH v7 " Li Zhang 0 siblings, 2 replies; 14+ messages in thread From: Li Zhang @ 2020-10-05 9:31 UTC (permalink / raw) To: dekelp, orika, viacheslavo, matan; +Cc: dev, thomas, rasland PRM expose fields "Icmp_header_data" in IPv4 ICMP. Update ICMP mask parameter with ICMP identifier and sequence number fields. ICMP sequence number spec with mask, Icmp_header_data low 16 bits are set. ICMP identifier spec with mask, Icmp_header_data high 16 bits are set. Signed-off-by: Li Zhang <lizh@nvidia.com> --- doc/guides/nics/mlx5.rst | 4 ++-- doc/guides/rel_notes/release_20_11.rst | 2 +- drivers/net/mlx5/mlx5_flow.c | 10 ++++++++-- drivers/net/mlx5/mlx5_flow_dv.c | 12 ++++++++++++ 4 files changed, 23 insertions(+), 5 deletions(-) diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst index 211c0c5a6c..576dbe5efd 100644 --- a/doc/guides/nics/mlx5.rst +++ b/doc/guides/nics/mlx5.rst @@ -288,7 +288,7 @@ Limitations - The input buffer, providing the removal size, is not validated. - The buffer size must match the length of the headers to be removed. -- ICMP/ICMP6 code/type matching, IP-in-IP and MPLS flow matching are all +- ICMP(code/type/identifier/sequence number) / ICMP6(code/type) matching, IP-in-IP and MPLS flow matching are all mutually exclusive features which cannot be supported together (see :ref:`mlx5_firmware_config`). @@ -1009,7 +1009,7 @@ Below are some firmware configurations listed. FLEX_PARSER_PROFILE_ENABLE=1 -- enable ICMP/ICMP6 code/type fields matching:: +- enable ICMP(code/type/identifier/sequence number) / ICMP6(code/type) fields matching:: FLEX_PARSER_PROFILE_ENABLE=2 diff --git a/doc/guides/rel_notes/release_20_11.rst b/doc/guides/rel_notes/release_20_11.rst index c6642f5f94..791f133d8f 100644 --- a/doc/guides/rel_notes/release_20_11.rst +++ b/doc/guides/rel_notes/release_20_11.rst @@ -73,7 +73,7 @@ New Features * Added flag action. * Added raw encap/decap actions. * Added VXLAN encap/decap actions. - * Added ICMP and ICMP6 matching items. + * Added ICMP(code/type/identifier/sequence number) and ICMP6(code/type) matching items. * Added option to set port mask for insertion/deletion: ``--portmask=N`` where N represents the hexadecimal bitmask of ports used. diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c index 416505f1c8..3cabfd4627 100644 --- a/drivers/net/mlx5/mlx5_flow.c +++ b/drivers/net/mlx5/mlx5_flow.c @@ -1303,6 +1303,12 @@ mlx5_flow_validate_item_icmp(const struct rte_flow_item *item, struct rte_flow_error *error) { const struct rte_flow_item_icmp *mask = item->mask; + const struct rte_flow_item_icmp nic_mask = { + .hdr.icmp_type = 0xff, + .hdr.icmp_code = 0xff, + .hdr.icmp_ident = RTE_BE16(0xffff), + .hdr.icmp_seq_nb = RTE_BE16(0xffff), + }; const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 : MLX5_FLOW_LAYER_OUTER_L3_IPV4; @@ -1325,10 +1331,10 @@ mlx5_flow_validate_item_icmp(const struct rte_flow_item *item, RTE_FLOW_ERROR_TYPE_ITEM, item, "multiple L4 layers not supported"); if (!mask) - mask = &rte_flow_item_icmp_mask; + mask = &nic_mask; ret = mlx5_flow_item_acceptable (item, (const uint8_t *)mask, - (const uint8_t *)&rte_flow_item_icmp_mask, + (const uint8_t *)&nic_mask, sizeof(struct rte_flow_item_icmp), error); if (ret < 0) return ret; diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index 3819cdb266..73361eef12 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -7378,6 +7378,8 @@ flow_dv_translate_item_icmp(void *matcher, void *key, { const struct rte_flow_item_icmp *icmp_m = item->mask; const struct rte_flow_item_icmp *icmp_v = item->spec; + uint32_t icmp_header_data_m = 0; + uint32_t icmp_header_data_v = 0; void *headers_m; void *headers_v; void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher, @@ -7412,6 +7414,16 @@ flow_dv_translate_item_icmp(void *matcher, void *key, icmp_m->hdr.icmp_code); MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code, icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code); + icmp_header_data_m = rte_be_to_cpu_16(icmp_m->hdr.icmp_seq_nb); + icmp_header_data_m |= rte_be_to_cpu_16(icmp_m->hdr.icmp_ident) << 16; + if (icmp_header_data_m) { + icmp_header_data_v = rte_be_to_cpu_16(icmp_v->hdr.icmp_seq_nb); + icmp_header_data_v |= rte_be_to_cpu_16(icmp_v->hdr.icmp_ident) << 16; + MLX5_SET(fte_match_set_misc3, misc3_m, icmp_header_data, + icmp_header_data_m); + MLX5_SET(fte_match_set_misc3, misc3_v, icmp_header_data, + icmp_header_data_v & icmp_header_data_m); + } } /** -- 2.21.0 ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [dpdk-dev] [PATCH v6 1/1] net/mlx5: support match ICMP identifier fields 2020-10-05 9:31 ` [dpdk-dev] [PATCH v6 " Li Zhang @ 2020-10-05 10:33 ` Ori Kam 2020-10-06 5:12 ` Li Zhang 2020-10-09 6:01 ` [dpdk-dev] [PATCH v7 " Li Zhang 1 sibling, 1 reply; 14+ messages in thread From: Ori Kam @ 2020-10-05 10:33 UTC (permalink / raw) To: Li Zhang, Dekel Peled, Slava Ovsiienko, Matan Azrad Cc: dev, NBU-Contact-Thomas Monjalon, Raslan Darawsheh Hi Li, > -----Original Message----- > From: dev <dev-bounces@dpdk.org> On Behalf Of Li Zhang > Sent: Monday, October 5, 2020 12:32 PM > To: Dekel Peled <dekelp@nvidia.com>; Ori Kam <orika@nvidia.com>; Slava > Ovsiienko <viacheslavo@nvidia.com>; Matan Azrad <matan@nvidia.com> > Cc: dev@dpdk.org; NBU-Contact-Thomas Monjalon <thomas@monjalon.net>; > Raslan Darawsheh <rasland@nvidia.com> > Subject: [dpdk-dev] [PATCH v6 1/1] net/mlx5: support match ICMP identifier > fields > > PRM expose fields "Icmp_header_data" in IPv4 ICMP. > Update ICMP mask parameter with ICMP identifier and sequence number > fields. > ICMP sequence number spec with mask, Icmp_header_data low 16 bits are set. > ICMP identifier spec with mask, Icmp_header_data high 16 bits are set. > > Signed-off-by: Li Zhang <lizh@nvidia.com> > --- Acked-by: Ori Kam <orika@nvidia.com> Thanks, Ori ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [dpdk-dev] [PATCH v6 1/1] net/mlx5: support match ICMP identifier fields 2020-10-05 10:33 ` Ori Kam @ 2020-10-06 5:12 ` Li Zhang 2020-10-06 12:07 ` Ori Kam 0 siblings, 1 reply; 14+ messages in thread From: Li Zhang @ 2020-10-06 5:12 UTC (permalink / raw) To: Ori Kam, Dekel Peled, Slava Ovsiienko, Matan Azrad Cc: dev, NBU-Contact-Thomas Monjalon, Raslan Darawsheh Hi Ori, What's your comment? I can not find it in last mail. Can you help give more detail about it? Thanks, Regards, Li Zhang > -----Original Message----- > From: Ori Kam <orika@nvidia.com> > Sent: Monday, October 5, 2020 6:33 PM > To: Li Zhang <lizh@nvidia.com>; Dekel Peled <dekelp@nvidia.com>; Slava > Ovsiienko <viacheslavo@nvidia.com>; Matan Azrad <matan@nvidia.com> > Cc: dev@dpdk.org; NBU-Contact-Thomas Monjalon <thomas@monjalon.net>; > Raslan Darawsheh <rasland@nvidia.com> > Subject: RE: [dpdk-dev] [PATCH v6 1/1] net/mlx5: support match ICMP > identifier fields > > Hi Li, > > > -----Original Message----- > > From: dev <dev-bounces@dpdk.org> On Behalf Of Li Zhang > > Sent: Monday, October 5, 2020 12:32 PM > > To: Dekel Peled <dekelp@nvidia.com>; Ori Kam <orika@nvidia.com>; Slava > > Ovsiienko <viacheslavo@nvidia.com>; Matan Azrad <matan@nvidia.com> > > Cc: dev@dpdk.org; NBU-Contact-Thomas Monjalon > <thomas@monjalon.net>; > > Raslan Darawsheh <rasland@nvidia.com> > > Subject: [dpdk-dev] [PATCH v6 1/1] net/mlx5: support match ICMP > > identifier fields > > > > PRM expose fields "Icmp_header_data" in IPv4 ICMP. > > Update ICMP mask parameter with ICMP identifier and sequence number > > fields. > > ICMP sequence number spec with mask, Icmp_header_data low 16 bits are > set. > > ICMP identifier spec with mask, Icmp_header_data high 16 bits are set. > > > > Signed-off-by: Li Zhang <lizh@nvidia.com> > > --- > > Acked-by: Ori Kam <orika@nvidia.com> > Thanks, > Ori ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [dpdk-dev] [PATCH v6 1/1] net/mlx5: support match ICMP identifier fields 2020-10-06 5:12 ` Li Zhang @ 2020-10-06 12:07 ` Ori Kam 2020-10-07 6:08 ` Li Zhang 0 siblings, 1 reply; 14+ messages in thread From: Ori Kam @ 2020-10-06 12:07 UTC (permalink / raw) To: Li Zhang, Dekel Peled, Slava Ovsiienko, Matan Azrad Cc: dev, NBU-Contact-Thomas Monjalon, Raslan Darawsheh Hi Li There was no comment. I acked your patch. Thanks, Ori > -----Original Message----- > From: Li Zhang <lizh@nvidia.com> > Sent: Tuesday, October 6, 2020 8:12 AM > To: Ori Kam <orika@nvidia.com>; Dekel Peled <dekelp@nvidia.com>; Slava > Ovsiienko <viacheslavo@nvidia.com>; Matan Azrad <matan@nvidia.com> > Cc: dev@dpdk.org; NBU-Contact-Thomas Monjalon <thomas@monjalon.net>; > Raslan Darawsheh <rasland@nvidia.com> > Subject: RE: [dpdk-dev] [PATCH v6 1/1] net/mlx5: support match ICMP > identifier fields > > Hi Ori, > > What's your comment? > I can not find it in last mail. > Can you help give more detail about it? > > Thanks, > Regards, > Li Zhang > > > -----Original Message----- > > From: Ori Kam <orika@nvidia.com> > > Sent: Monday, October 5, 2020 6:33 PM > > To: Li Zhang <lizh@nvidia.com>; Dekel Peled <dekelp@nvidia.com>; Slava > > Ovsiienko <viacheslavo@nvidia.com>; Matan Azrad <matan@nvidia.com> > > Cc: dev@dpdk.org; NBU-Contact-Thomas Monjalon <thomas@monjalon.net>; > > Raslan Darawsheh <rasland@nvidia.com> > > Subject: RE: [dpdk-dev] [PATCH v6 1/1] net/mlx5: support match ICMP > > identifier fields > > > > Hi Li, > > > > > -----Original Message----- > > > From: dev <dev-bounces@dpdk.org> On Behalf Of Li Zhang > > > Sent: Monday, October 5, 2020 12:32 PM > > > To: Dekel Peled <dekelp@nvidia.com>; Ori Kam <orika@nvidia.com>; Slava > > > Ovsiienko <viacheslavo@nvidia.com>; Matan Azrad <matan@nvidia.com> > > > Cc: dev@dpdk.org; NBU-Contact-Thomas Monjalon > > <thomas@monjalon.net>; > > > Raslan Darawsheh <rasland@nvidia.com> > > > Subject: [dpdk-dev] [PATCH v6 1/1] net/mlx5: support match ICMP > > > identifier fields > > > > > > PRM expose fields "Icmp_header_data" in IPv4 ICMP. > > > Update ICMP mask parameter with ICMP identifier and sequence number > > > fields. > > > ICMP sequence number spec with mask, Icmp_header_data low 16 bits are > > set. > > > ICMP identifier spec with mask, Icmp_header_data high 16 bits are set. > > > > > > Signed-off-by: Li Zhang <lizh@nvidia.com> > > > --- > > > > Acked-by: Ori Kam <orika@nvidia.com> > > Thanks, > > Ori ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [dpdk-dev] [PATCH v6 1/1] net/mlx5: support match ICMP identifier fields 2020-10-06 12:07 ` Ori Kam @ 2020-10-07 6:08 ` Li Zhang 0 siblings, 0 replies; 14+ messages in thread From: Li Zhang @ 2020-10-07 6:08 UTC (permalink / raw) To: Ori Kam, Dekel Peled, Slava Ovsiienko, Matan Azrad Cc: dev, NBU-Contact-Thomas Monjalon, Raslan Darawsheh Hi Ori, My latest patch V6 as below: Please help review it. https://patchwork.dpdk.org/patch/79613/ Thanks, Regards, Li Zhang > -----Original Message----- > From: Ori Kam <orika@nvidia.com> > Sent: Tuesday, October 6, 2020 8:07 PM > To: Li Zhang <lizh@nvidia.com>; Dekel Peled <dekelp@nvidia.com>; Slava > Ovsiienko <viacheslavo@nvidia.com>; Matan Azrad <matan@nvidia.com> > Cc: dev@dpdk.org; NBU-Contact-Thomas Monjalon <thomas@monjalon.net>; > Raslan Darawsheh <rasland@nvidia.com> > Subject: RE: [dpdk-dev] [PATCH v6 1/1] net/mlx5: support match ICMP > identifier fields > > Hi Li > > There was no comment. I acked your patch. > > Thanks, > Ori > > > -----Original Message----- > > From: Li Zhang <lizh@nvidia.com> > > Sent: Tuesday, October 6, 2020 8:12 AM > > To: Ori Kam <orika@nvidia.com>; Dekel Peled <dekelp@nvidia.com>; Slava > > Ovsiienko <viacheslavo@nvidia.com>; Matan Azrad <matan@nvidia.com> > > Cc: dev@dpdk.org; NBU-Contact-Thomas Monjalon > <thomas@monjalon.net>; > > Raslan Darawsheh <rasland@nvidia.com> > > Subject: RE: [dpdk-dev] [PATCH v6 1/1] net/mlx5: support match ICMP > > identifier fields > > > > Hi Ori, > > > > What's your comment? > > I can not find it in last mail. > > Can you help give more detail about it? > > > > Thanks, > > Regards, > > Li Zhang > > > > > -----Original Message----- > > > From: Ori Kam <orika@nvidia.com> > > > Sent: Monday, October 5, 2020 6:33 PM > > > To: Li Zhang <lizh@nvidia.com>; Dekel Peled <dekelp@nvidia.com>; > > > Slava Ovsiienko <viacheslavo@nvidia.com>; Matan Azrad > > > <matan@nvidia.com> > > > Cc: dev@dpdk.org; NBU-Contact-Thomas Monjalon > <thomas@monjalon.net>; > > > Raslan Darawsheh <rasland@nvidia.com> > > > Subject: RE: [dpdk-dev] [PATCH v6 1/1] net/mlx5: support match ICMP > > > identifier fields > > > > > > Hi Li, > > > > > > > -----Original Message----- > > > > From: dev <dev-bounces@dpdk.org> On Behalf Of Li Zhang > > > > Sent: Monday, October 5, 2020 12:32 PM > > > > To: Dekel Peled <dekelp@nvidia.com>; Ori Kam <orika@nvidia.com>; > > > > Slava Ovsiienko <viacheslavo@nvidia.com>; Matan Azrad > > > > <matan@nvidia.com> > > > > Cc: dev@dpdk.org; NBU-Contact-Thomas Monjalon > > > <thomas@monjalon.net>; > > > > Raslan Darawsheh <rasland@nvidia.com> > > > > Subject: [dpdk-dev] [PATCH v6 1/1] net/mlx5: support match ICMP > > > > identifier fields > > > > > > > > PRM expose fields "Icmp_header_data" in IPv4 ICMP. > > > > Update ICMP mask parameter with ICMP identifier and sequence > > > > number fields. > > > > ICMP sequence number spec with mask, Icmp_header_data low 16 bits > > > > are > > > set. > > > > ICMP identifier spec with mask, Icmp_header_data high 16 bits are set. > > > > > > > > Signed-off-by: Li Zhang <lizh@nvidia.com> > > > > --- > > > > > > Acked-by: Ori Kam <orika@nvidia.com> Thanks, Ori ^ permalink raw reply [flat|nested] 14+ messages in thread
* [dpdk-dev] [PATCH v7 1/1] net/mlx5: support match ICMP identifier fields 2020-10-05 9:31 ` [dpdk-dev] [PATCH v6 " Li Zhang 2020-10-05 10:33 ` Ori Kam @ 2020-10-09 6:01 ` Li Zhang 2020-10-09 6:06 ` [dpdk-dev] [PATCH v8 " Li Zhang 1 sibling, 1 reply; 14+ messages in thread From: Li Zhang @ 2020-10-09 6:01 UTC (permalink / raw) To: dekelp, orika, viacheslavo, matan; +Cc: dev, thomas, rasland PRM expose fields "Icmp_header_data" in IPv4 ICMP. Update ICMP mask parameter with ICMP identifier and sequence number fields. ICMP sequence number spec with mask, Icmp_header_data low 16 bits are set. ICMP identifier spec with mask, Icmp_header_data high 16 bits are set. Signed-off-by: Li Zhang <lizh@nvidia.com> Acked-by: Ori Kam <orika@nvidia.com> --- doc/guides/nics/mlx5.rst | 4 ++-- doc/guides/rel_notes/release_20_11.rst | 2 +- drivers/net/mlx5/mlx5_flow.c | 10 ++++++++-- drivers/net/mlx5/mlx5_flow_dv.c | 13 +++++++++++++ 4 files changed, 24 insertions(+), 5 deletions(-) diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst index b0614ae335..a174cdd5f5 100644 --- a/doc/guides/nics/mlx5.rst +++ b/doc/guides/nics/mlx5.rst @@ -288,7 +288,7 @@ Limitations - The input buffer, providing the removal size, is not validated. - The buffer size must match the length of the headers to be removed. -- ICMP/ICMP6 code/type matching, IP-in-IP and MPLS flow matching are all +- ICMP(code/type/identifier/sequence number) / ICMP6(code/type) matching, IP-in-IP and MPLS flow matching are all mutually exclusive features which cannot be supported together (see :ref:`mlx5_firmware_config`). @@ -1009,7 +1009,7 @@ Below are some firmware configurations listed. FLEX_PARSER_PROFILE_ENABLE=1 -- enable ICMP/ICMP6 code/type fields matching:: +- enable ICMP(code/type/identifier/sequence number) / ICMP6(code/type) fields matching:: FLEX_PARSER_PROFILE_ENABLE=2 diff --git a/doc/guides/rel_notes/release_20_11.rst b/doc/guides/rel_notes/release_20_11.rst index b0637640d1..e22e0c3981 100644 --- a/doc/guides/rel_notes/release_20_11.rst +++ b/doc/guides/rel_notes/release_20_11.rst @@ -102,7 +102,7 @@ New Features * Added flag action. * Added raw encap/decap actions. * Added VXLAN encap/decap actions. - * Added ICMP and ICMP6 matching items. + * Added ICMP(code/type/identifier/sequence number) and ICMP6(code/type) matching items. * Added option to set port mask for insertion/deletion: ``--portmask=N`` where N represents the hexadecimal bitmask of ports used. diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c index 691eb9a3cd..0a54818c0c 100644 --- a/drivers/net/mlx5/mlx5_flow.c +++ b/drivers/net/mlx5/mlx5_flow.c @@ -1629,6 +1629,12 @@ mlx5_flow_validate_item_icmp(const struct rte_flow_item *item, struct rte_flow_error *error) { const struct rte_flow_item_icmp *mask = item->mask; + const struct rte_flow_item_icmp nic_mask = { + .hdr.icmp_type = 0xff, + .hdr.icmp_code = 0xff, + .hdr.icmp_ident = RTE_BE16(0xffff), + .hdr.icmp_seq_nb = RTE_BE16(0xffff), + }; const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 : MLX5_FLOW_LAYER_OUTER_L3_IPV4; @@ -1651,10 +1657,10 @@ mlx5_flow_validate_item_icmp(const struct rte_flow_item *item, RTE_FLOW_ERROR_TYPE_ITEM, item, "multiple L4 layers not supported"); if (!mask) - mask = &rte_flow_item_icmp_mask; + mask = &nic_mask; ret = mlx5_flow_item_acceptable (item, (const uint8_t *)mask, - (const uint8_t *)&rte_flow_item_icmp_mask, + (const uint8_t *)&nic_mask, sizeof(struct rte_flow_item_icmp), error); if (ret < 0) return ret; diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index 79fdf34c0e..295d32b1f3 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -7378,6 +7378,8 @@ flow_dv_translate_item_icmp(void *matcher, void *key, { const struct rte_flow_item_icmp *icmp_m = item->mask; const struct rte_flow_item_icmp *icmp_v = item->spec; + uint32_t icmp_header_data_m = 0; + uint32_t icmp_header_data_v = 0; void *headers_m; void *headers_v; void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher, @@ -7412,6 +7414,17 @@ flow_dv_translate_item_icmp(void *matcher, void *key, icmp_m->hdr.icmp_code); MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code, icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code); + icmp_header_data_m = rte_be_to_cpu_16(icmp_m->hdr.icmp_seq_nb); + icmp_header_data_m |= rte_be_to_cpu_16(icmp_m->hdr.icmp_ident) << 16; + if (icmp_header_data_m) { + icmp_header_data_v = rte_be_to_cpu_16(icmp_v->hdr.icmp_seq_nb); + icmp_header_data_v |= + rte_be_to_cpu_16(icmp_v->hdr.icmp_ident) << 16; + MLX5_SET(fte_match_set_misc3, misc3_m, icmp_header_data, + icmp_header_data_m); + MLX5_SET(fte_match_set_misc3, misc3_v, icmp_header_data, + icmp_header_data_v & icmp_header_data_m); + } } /** -- 2.21.0 ^ permalink raw reply [flat|nested] 14+ messages in thread
* [dpdk-dev] [PATCH v8 1/1] net/mlx5: support match ICMP identifier fields 2020-10-09 6:01 ` [dpdk-dev] [PATCH v7 " Li Zhang @ 2020-10-09 6:06 ` Li Zhang 2020-10-09 6:11 ` [dpdk-dev] [PATCH v9 " Li Zhang 0 siblings, 1 reply; 14+ messages in thread From: Li Zhang @ 2020-10-09 6:06 UTC (permalink / raw) To: dekelp, orika, viacheslavo, matan; +Cc: dev, thomas, rasland PRM expose fields "Icmp_header_data" in IPv4 ICMP. Update ICMP mask parameter with ICMP identifier and sequence number fields. ICMP sequence number spec with mask, Icmp_header_data low 16 bits are set. ICMP identifier spec with mask, Icmp_header_data high 16 bits are set. Signed-off-by: Li Zhang <lizh@nvidia.com> Acked-by: Ori Kam <orika@nvidia.com> --- doc/guides/nics/mlx5.rst | 4 ++-- doc/guides/rel_notes/release_20_11.rst | 2 +- drivers/net/mlx5/mlx5_flow.c | 10 ++++++++-- drivers/net/mlx5/mlx5_flow_dv.c | 13 +++++++++++++ 4 files changed, 24 insertions(+), 5 deletions(-) diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst index b0614ae335..a174cdd5f5 100644 --- a/doc/guides/nics/mlx5.rst +++ b/doc/guides/nics/mlx5.rst @@ -288,7 +288,7 @@ Limitations - The input buffer, providing the removal size, is not validated. - The buffer size must match the length of the headers to be removed. -- ICMP/ICMP6 code/type matching, IP-in-IP and MPLS flow matching are all +- ICMP(code/type/identifier/sequence number) / ICMP6(code/type) matching, IP-in-IP and MPLS flow matching are all mutually exclusive features which cannot be supported together (see :ref:`mlx5_firmware_config`). @@ -1009,7 +1009,7 @@ Below are some firmware configurations listed. FLEX_PARSER_PROFILE_ENABLE=1 -- enable ICMP/ICMP6 code/type fields matching:: +- enable ICMP(code/type/identifier/sequence number) / ICMP6(code/type) fields matching:: FLEX_PARSER_PROFILE_ENABLE=2 diff --git a/doc/guides/rel_notes/release_20_11.rst b/doc/guides/rel_notes/release_20_11.rst index b0637640d1..e22e0c3981 100644 --- a/doc/guides/rel_notes/release_20_11.rst +++ b/doc/guides/rel_notes/release_20_11.rst @@ -102,7 +102,7 @@ New Features * Added flag action. * Added raw encap/decap actions. * Added VXLAN encap/decap actions. - * Added ICMP and ICMP6 matching items. + * Added ICMP(code/type/identifier/sequence number) and ICMP6(code/type) matching items. * Added option to set port mask for insertion/deletion: ``--portmask=N`` where N represents the hexadecimal bitmask of ports used. diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c index 691eb9a3cd..0a54818c0c 100644 --- a/drivers/net/mlx5/mlx5_flow.c +++ b/drivers/net/mlx5/mlx5_flow.c @@ -1629,6 +1629,12 @@ mlx5_flow_validate_item_icmp(const struct rte_flow_item *item, struct rte_flow_error *error) { const struct rte_flow_item_icmp *mask = item->mask; + const struct rte_flow_item_icmp nic_mask = { + .hdr.icmp_type = 0xff, + .hdr.icmp_code = 0xff, + .hdr.icmp_ident = RTE_BE16(0xffff), + .hdr.icmp_seq_nb = RTE_BE16(0xffff), + }; const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 : MLX5_FLOW_LAYER_OUTER_L3_IPV4; @@ -1651,10 +1657,10 @@ mlx5_flow_validate_item_icmp(const struct rte_flow_item *item, RTE_FLOW_ERROR_TYPE_ITEM, item, "multiple L4 layers not supported"); if (!mask) - mask = &rte_flow_item_icmp_mask; + mask = &nic_mask; ret = mlx5_flow_item_acceptable (item, (const uint8_t *)mask, - (const uint8_t *)&rte_flow_item_icmp_mask, + (const uint8_t *)&nic_mask, sizeof(struct rte_flow_item_icmp), error); if (ret < 0) return ret; diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index 79fdf34c0e..8e9eaf921b 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -7378,6 +7378,8 @@ flow_dv_translate_item_icmp(void *matcher, void *key, { const struct rte_flow_item_icmp *icmp_m = item->mask; const struct rte_flow_item_icmp *icmp_v = item->spec; + uint32_t icmp_header_data_m = 0; + uint32_t icmp_header_data_v = 0; void *headers_m; void *headers_v; void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher, @@ -7412,6 +7414,17 @@ flow_dv_translate_item_icmp(void *matcher, void *key, icmp_m->hdr.icmp_code); MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code, icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code); + icmp_header_data_m = rte_be_to_cpu_16(icmp_m->hdr.icmp_seq_nb); + icmp_header_data_m |= rte_be_to_cpu_16(icmp_m->hdr.icmp_ident) << 16; + if (icmp_header_data_m) { + icmp_header_data_v = rte_be_to_cpu_16(icmp_v->hdr.icmp_seq_nb); + icmp_header_data_v |= + rte_be_to_cpu_16(icmp_v->hdr.icmp_ident) << 16; + MLX5_SET(fte_match_set_misc3, misc3_m, icmp_header_data, + icmp_header_data_m); + MLX5_SET(fte_match_set_misc3, misc3_v, icmp_header_data, + icmp_header_data_v & icmp_header_data_m); + } } /** -- 2.21.0 ^ permalink raw reply [flat|nested] 14+ messages in thread
* [dpdk-dev] [PATCH v9 1/1] net/mlx5: support match ICMP identifier fields 2020-10-09 6:06 ` [dpdk-dev] [PATCH v8 " Li Zhang @ 2020-10-09 6:11 ` Li Zhang 2020-10-11 10:19 ` Raslan Darawsheh 0 siblings, 1 reply; 14+ messages in thread From: Li Zhang @ 2020-10-09 6:11 UTC (permalink / raw) To: dekelp, orika, viacheslavo, matan; +Cc: dev, thomas, rasland PRM expose fields "Icmp_header_data" in IPv4 ICMP. Update ICMP mask parameter with ICMP identifier and sequence number fields. ICMP sequence number spec with mask, Icmp_header_data low 16 bits are set. ICMP identifier spec with mask, Icmp_header_data high 16 bits are set. Signed-off-by: Li Zhang <lizh@nvidia.com> Acked-by: Ori Kam <orika@nvidia.com> --- doc/guides/nics/mlx5.rst | 4 ++-- doc/guides/rel_notes/release_20_11.rst | 2 +- drivers/net/mlx5/mlx5_flow.c | 10 ++++++++-- drivers/net/mlx5/mlx5_flow_dv.c | 13 +++++++++++++ 4 files changed, 24 insertions(+), 5 deletions(-) diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst index b0614ae335..a174cdd5f5 100644 --- a/doc/guides/nics/mlx5.rst +++ b/doc/guides/nics/mlx5.rst @@ -288,7 +288,7 @@ Limitations - The input buffer, providing the removal size, is not validated. - The buffer size must match the length of the headers to be removed. -- ICMP/ICMP6 code/type matching, IP-in-IP and MPLS flow matching are all +- ICMP(code/type/identifier/sequence number) / ICMP6(code/type) matching, IP-in-IP and MPLS flow matching are all mutually exclusive features which cannot be supported together (see :ref:`mlx5_firmware_config`). @@ -1009,7 +1009,7 @@ Below are some firmware configurations listed. FLEX_PARSER_PROFILE_ENABLE=1 -- enable ICMP/ICMP6 code/type fields matching:: +- enable ICMP(code/type/identifier/sequence number) / ICMP6(code/type) fields matching:: FLEX_PARSER_PROFILE_ENABLE=2 diff --git a/doc/guides/rel_notes/release_20_11.rst b/doc/guides/rel_notes/release_20_11.rst index b0637640d1..e22e0c3981 100644 --- a/doc/guides/rel_notes/release_20_11.rst +++ b/doc/guides/rel_notes/release_20_11.rst @@ -102,7 +102,7 @@ New Features * Added flag action. * Added raw encap/decap actions. * Added VXLAN encap/decap actions. - * Added ICMP and ICMP6 matching items. + * Added ICMP(code/type/identifier/sequence number) and ICMP6(code/type) matching items. * Added option to set port mask for insertion/deletion: ``--portmask=N`` where N represents the hexadecimal bitmask of ports used. diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c index 691eb9a3cd..0a54818c0c 100644 --- a/drivers/net/mlx5/mlx5_flow.c +++ b/drivers/net/mlx5/mlx5_flow.c @@ -1629,6 +1629,12 @@ mlx5_flow_validate_item_icmp(const struct rte_flow_item *item, struct rte_flow_error *error) { const struct rte_flow_item_icmp *mask = item->mask; + const struct rte_flow_item_icmp nic_mask = { + .hdr.icmp_type = 0xff, + .hdr.icmp_code = 0xff, + .hdr.icmp_ident = RTE_BE16(0xffff), + .hdr.icmp_seq_nb = RTE_BE16(0xffff), + }; const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 : MLX5_FLOW_LAYER_OUTER_L3_IPV4; @@ -1651,10 +1657,10 @@ mlx5_flow_validate_item_icmp(const struct rte_flow_item *item, RTE_FLOW_ERROR_TYPE_ITEM, item, "multiple L4 layers not supported"); if (!mask) - mask = &rte_flow_item_icmp_mask; + mask = &nic_mask; ret = mlx5_flow_item_acceptable (item, (const uint8_t *)mask, - (const uint8_t *)&rte_flow_item_icmp_mask, + (const uint8_t *)&nic_mask, sizeof(struct rte_flow_item_icmp), error); if (ret < 0) return ret; diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index 79fdf34c0e..2bbfcea1ed 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -7378,6 +7378,8 @@ flow_dv_translate_item_icmp(void *matcher, void *key, { const struct rte_flow_item_icmp *icmp_m = item->mask; const struct rte_flow_item_icmp *icmp_v = item->spec; + uint32_t icmp_header_data_m = 0; + uint32_t icmp_header_data_v = 0; void *headers_m; void *headers_v; void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher, @@ -7412,6 +7414,17 @@ flow_dv_translate_item_icmp(void *matcher, void *key, icmp_m->hdr.icmp_code); MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code, icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code); + icmp_header_data_m = rte_be_to_cpu_16(icmp_m->hdr.icmp_seq_nb); + icmp_header_data_m |= rte_be_to_cpu_16(icmp_m->hdr.icmp_ident) << 16; + if (icmp_header_data_m) { + icmp_header_data_v = rte_be_to_cpu_16(icmp_v->hdr.icmp_seq_nb); + icmp_header_data_v |= + rte_be_to_cpu_16(icmp_v->hdr.icmp_ident) << 16; + MLX5_SET(fte_match_set_misc3, misc3_m, icmp_header_data, + icmp_header_data_m); + MLX5_SET(fte_match_set_misc3, misc3_v, icmp_header_data, + icmp_header_data_v & icmp_header_data_m); + } } /** -- 2.21.0 ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [dpdk-dev] [PATCH v9 1/1] net/mlx5: support match ICMP identifier fields 2020-10-09 6:11 ` [dpdk-dev] [PATCH v9 " Li Zhang @ 2020-10-11 10:19 ` Raslan Darawsheh 0 siblings, 0 replies; 14+ messages in thread From: Raslan Darawsheh @ 2020-10-11 10:19 UTC (permalink / raw) To: Li Zhang, Dekel Peled, Ori Kam, Slava Ovsiienko, Matan Azrad Cc: dev, NBU-Contact-Thomas Monjalon Hi, > -----Original Message----- > From: Li Zhang <lizh@nvidia.com> > Sent: Friday, October 9, 2020 9:12 AM > To: Dekel Peled <dekelp@nvidia.com>; Ori Kam <orika@nvidia.com>; Slava > Ovsiienko <viacheslavo@nvidia.com>; Matan Azrad <matan@nvidia.com> > Cc: dev@dpdk.org; NBU-Contact-Thomas Monjalon > <thomas@monjalon.net>; Raslan Darawsheh <rasland@nvidia.com> > Subject: [PATCH v9 1/1] net/mlx5: support match ICMP identifier fields > > PRM expose fields "Icmp_header_data" in IPv4 ICMP. > Update ICMP mask parameter with ICMP identifier and sequence number > fields. > ICMP sequence number spec with mask, Icmp_header_data low 16 bits are > set. > ICMP identifier spec with mask, Icmp_header_data high 16 bits are set. > > Signed-off-by: Li Zhang <lizh@nvidia.com> > Acked-by: Ori Kam <orika@nvidia.com> > --- > doc/guides/nics/mlx5.rst | 4 ++-- > doc/guides/rel_notes/release_20_11.rst | 2 +- > drivers/net/mlx5/mlx5_flow.c | 10 ++++++++-- > drivers/net/mlx5/mlx5_flow_dv.c | 13 +++++++++++++ > 4 files changed, 24 insertions(+), 5 deletions(-) > > diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst > index b0614ae335..a174cdd5f5 100644 > --- a/doc/guides/nics/mlx5.rst > +++ b/doc/guides/nics/mlx5.rst > @@ -288,7 +288,7 @@ Limitations > - The input buffer, providing the removal size, is not validated. > - The buffer size must match the length of the headers to be removed. > > -- ICMP/ICMP6 code/type matching, IP-in-IP and MPLS flow matching are all > +- ICMP(code/type/identifier/sequence number) / ICMP6(code/type) > matching, IP-in-IP and MPLS flow matching are all > mutually exclusive features which cannot be supported together > (see :ref:`mlx5_firmware_config`). > > @@ -1009,7 +1009,7 @@ Below are some firmware configurations listed. > > FLEX_PARSER_PROFILE_ENABLE=1 > > -- enable ICMP/ICMP6 code/type fields matching:: > +- enable ICMP(code/type/identifier/sequence number) / > ICMP6(code/type) fields matching:: > > FLEX_PARSER_PROFILE_ENABLE=2 > > diff --git a/doc/guides/rel_notes/release_20_11.rst > b/doc/guides/rel_notes/release_20_11.rst > index b0637640d1..e22e0c3981 100644 > --- a/doc/guides/rel_notes/release_20_11.rst > +++ b/doc/guides/rel_notes/release_20_11.rst > @@ -102,7 +102,7 @@ New Features > * Added flag action. > * Added raw encap/decap actions. > * Added VXLAN encap/decap actions. > - * Added ICMP and ICMP6 matching items. > + * Added ICMP(code/type/identifier/sequence number) and > ICMP6(code/type) matching items. > * Added option to set port mask for insertion/deletion: > ``--portmask=N`` > where N represents the hexadecimal bitmask of ports used. > diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c > index 691eb9a3cd..0a54818c0c 100644 > --- a/drivers/net/mlx5/mlx5_flow.c > +++ b/drivers/net/mlx5/mlx5_flow.c > @@ -1629,6 +1629,12 @@ mlx5_flow_validate_item_icmp(const struct > rte_flow_item *item, > struct rte_flow_error *error) > { > const struct rte_flow_item_icmp *mask = item->mask; > + const struct rte_flow_item_icmp nic_mask = { > + .hdr.icmp_type = 0xff, > + .hdr.icmp_code = 0xff, > + .hdr.icmp_ident = RTE_BE16(0xffff), > + .hdr.icmp_seq_nb = RTE_BE16(0xffff), > + }; > const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); > const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 : > MLX5_FLOW_LAYER_OUTER_L3_IPV4; > @@ -1651,10 +1657,10 @@ mlx5_flow_validate_item_icmp(const struct > rte_flow_item *item, > RTE_FLOW_ERROR_TYPE_ITEM, > item, > "multiple L4 layers not supported"); > if (!mask) > - mask = &rte_flow_item_icmp_mask; > + mask = &nic_mask; > ret = mlx5_flow_item_acceptable > (item, (const uint8_t *)mask, > - (const uint8_t *)&rte_flow_item_icmp_mask, > + (const uint8_t *)&nic_mask, > sizeof(struct rte_flow_item_icmp), error); > if (ret < 0) > return ret; > diff --git a/drivers/net/mlx5/mlx5_flow_dv.c > b/drivers/net/mlx5/mlx5_flow_dv.c > index 79fdf34c0e..2bbfcea1ed 100644 > --- a/drivers/net/mlx5/mlx5_flow_dv.c > +++ b/drivers/net/mlx5/mlx5_flow_dv.c > @@ -7378,6 +7378,8 @@ flow_dv_translate_item_icmp(void *matcher, void > *key, > { > const struct rte_flow_item_icmp *icmp_m = item->mask; > const struct rte_flow_item_icmp *icmp_v = item->spec; > + uint32_t icmp_header_data_m = 0; > + uint32_t icmp_header_data_v = 0; > void *headers_m; > void *headers_v; > void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher, > @@ -7412,6 +7414,17 @@ flow_dv_translate_item_icmp(void *matcher, > void *key, > icmp_m->hdr.icmp_code); > MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code, > icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code); > + icmp_header_data_m = rte_be_to_cpu_16(icmp_m- > >hdr.icmp_seq_nb); > + icmp_header_data_m |= rte_be_to_cpu_16(icmp_m- > >hdr.icmp_ident) << 16; > + if (icmp_header_data_m) { > + icmp_header_data_v = rte_be_to_cpu_16(icmp_v- > >hdr.icmp_seq_nb); > + icmp_header_data_v |= > + rte_be_to_cpu_16(icmp_v->hdr.icmp_ident) << 16; > + MLX5_SET(fte_match_set_misc3, misc3_m, > icmp_header_data, > + icmp_header_data_m); > + MLX5_SET(fte_match_set_misc3, misc3_v, > icmp_header_data, > + icmp_header_data_v & icmp_header_data_m); > + } > } > > /** > -- > 2.21.0 Patch applied to next-net-mlx, Kindest regards, Raslan Darawsheh ^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2020-10-11 10:19 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz / follow: Atom feed)
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2020-10-02 8:40 ` [dpdk-dev] [PATCH v4 1/1] net/mlx5: support match ICMP identifier fields Li Zhang
2020-10-04 11:59 ` Ori Kam
2020-10-05 9:20 ` Li Zhang
2020-10-05 9:41 ` Li Zhang
2020-10-05 9:18 ` [dpdk-dev] [PATCH v5 " Li Zhang
2020-10-05 9:31 ` [dpdk-dev] [PATCH v6 " Li Zhang
2020-10-05 10:33 ` Ori Kam
2020-10-06 5:12 ` Li Zhang
2020-10-06 12:07 ` Ori Kam
2020-10-07 6:08 ` Li Zhang
2020-10-09 6:01 ` [dpdk-dev] [PATCH v7 " Li Zhang
2020-10-09 6:06 ` [dpdk-dev] [PATCH v8 " Li Zhang
2020-10-09 6:11 ` [dpdk-dev] [PATCH v9 " Li Zhang
2020-10-11 10:19 ` Raslan Darawsheh
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