From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by dpdk.org (Postfix) with ESMTP id 4BE98590C for ; Wed, 18 Jun 2014 20:17:52 +0200 (CEST) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga102.jf.intel.com with ESMTP; 18 Jun 2014 11:12:09 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.01,501,1400050800"; d="scan'208";a="530581165" Received: from irsmsx103.ger.corp.intel.com ([163.33.3.157]) by orsmga001.jf.intel.com with ESMTP; 18 Jun 2014 11:17:19 -0700 Received: from irsmsx106.ger.corp.intel.com (163.33.3.31) by IRSMSX103.ger.corp.intel.com (163.33.3.157) with Microsoft SMTP Server (TLS) id 14.3.123.3; Wed, 18 Jun 2014 19:17:18 +0100 Received: from irsmsx103.ger.corp.intel.com ([169.254.3.58]) by IRSMSX106.ger.corp.intel.com ([169.254.8.14]) with mapi id 14.03.0123.003; Wed, 18 Jun 2014 19:17:18 +0100 From: "De Lara Guarch, Pablo" To: Shannon Zhao , "dev@dpdk.org" Thread-Topic: [dpdk-dev] [PATCH v3] cpu_layout.py: adjust output format to align Thread-Index: AQHPiqyXLnFtDhBk0EOfLhRct1d1IJt3LXzQ Date: Wed, 18 Jun 2014 18:17:18 +0000 Message-ID: References: <2140757.fj3Ic02JMu@xps13> <1403065095-11092-1-git-send-email-zhaoshenglong@huawei.com> In-Reply-To: <1403065095-11092-1-git-send-email-zhaoshenglong@huawei.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [163.33.239.181] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v3] cpu_layout.py: adjust output format to align X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 18 Jun 2014 18:17:52 -0000 > -----Original Message----- > From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Shannon Zhao > Sent: Wednesday, June 18, 2014 5:18 AM > To: dev@dpdk.org > Subject: [dpdk-dev] [PATCH v3] cpu_layout.py: adjust output format to ali= gn >=20 > Bug: when "core id" is greater than 9, the cpu_layout.py output doesn't a= lign. >=20 > Socket 0 Socket 1 > --------- --------- > Core 9 [4, 16] [10, 22] >=20 > Core 10 [5, 17] [11, 23] >=20 > Solution: adjust output format to align based on the maximum length of th= e > "core id" and "processor" >=20 > Socket 0 Socket 1 > -------- -------- > Core 9 [4, 16] [10, 22] >=20 > Core 10 [5, 17] [11, 23] >=20 > Signed-off-by: Shannon Zhao Acked-by: Pablo de Lara