From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by dpdk.org (Postfix) with ESMTP id 82B23A2F for ; Tue, 31 May 2016 13:29:30 +0200 (CEST) Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga103.jf.intel.com with ESMTP; 31 May 2016 04:29:30 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.26,395,1459839600"; d="scan'208";a="113361133" Received: from irsmsx107.ger.corp.intel.com ([163.33.3.99]) by fmsmga004.fm.intel.com with ESMTP; 31 May 2016 04:29:28 -0700 Received: from irsmsx108.ger.corp.intel.com ([169.254.11.183]) by IRSMSX107.ger.corp.intel.com ([169.254.10.96]) with mapi id 14.03.0248.002; Tue, 31 May 2016 12:29:27 +0100 From: "De Lara Guarch, Pablo" To: "Jain, Deepak K" , Thomas Monjalon , "Kusztal, ArkadiuszX" CC: "dev@dpdk.org" , "Trahe, Fiona" , "Griffin, John" Thread-Topic: [dpdk-dev] [PATCH] qat: change optimization flag for Intel QuickAssist Technology Thread-Index: AQHRrPD65UTgrFn0qEq/kqt0oMH5KZ/TBQNw Date: Tue, 31 May 2016 11:29:27 +0000 Message-ID: References: <1462872255-13100-1-git-send-email-arkadiuszx.kusztal@intel.com> <1802357.As1ss59lSu@xps13> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiMGQyYzQzMmQtZDlhZC00ODFmLWE5ZTUtZjg2MjgxMjA4MDZlIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX0lDIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE1LjkuNi42IiwiVHJ1c3RlZExhYmVsSGFzaCI6InZaT3hQb0Z4YzNvU3JlOXl3RkZNR29WeUgycDZ4S2J6NTVrZ2J0RGNGaXM9In0= x-ctpclassification: CTP_IC x-originating-ip: [163.33.239.182] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH] qat: change optimization flag for Intel QuickAssist Technology X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 31 May 2016 11:29:31 -0000 Hi Deepak/Arek, > -----Original Message----- > From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Jain, Deepak K > Sent: Friday, May 13, 2016 9:25 AM > To: Thomas Monjalon; Kusztal, ArkadiuszX > Cc: dev@dpdk.org; Trahe, Fiona; Griffin, John > Subject: Re: [dpdk-dev] [PATCH] qat: change optimization flag for Intel > QuickAssist Technology >=20 > Hi Thomas, >=20 > This change was made to fix the compilation issues arising when optimizat= ion > flag was changed. Hence its related to same optimization flag patch. > Do you want us to separate the Makefile and .c file change? >=20 I think you need to explain the change in the .c file and separate it to an= other patch, if it is not related to the Makefile change (and if it is rela= ted, consider creating a patchset, maybe). Thanks, Pablo > Regards, > Deepak >=20 > -----Original Message----- > From: Thomas Monjalon [mailto:thomas.monjalon@6wind.com] > Sent: Friday, May 13, 2016 9:18 AM > To: Kusztal, ArkadiuszX > Cc: dev@dpdk.org; Trahe, Fiona ; Griffin, John > ; Jain, Deepak K > Subject: Re: [dpdk-dev] [PATCH] qat: change optimization flag for Intel > QuickAssist Technology >=20 > 2016-05-10 10:24, Arek Kusztal: > > From: Arkadiusz Kusztal > > > > Changed to -O3 optimization flag in Intel QuickAssist Technology Makefi= le >=20 > There is another change below. Should it be a separate patch? >=20 > > --- a/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c > > +++ b/drivers/crypto/qat/qat_adf/qat_algs_build_desc.c > > @@ -616,10 +616,12 @@ int > qat_alg_aead_session_create_content_desc_auth(struct qat_session *cdesc, > > * Write (the length of AAD) into bytes 16-19 of state2 > > * in big-endian format. This field is 8 bytes > > */ > > - *(uint32_t *)&(hash->sha.state1[ > > + uint32_t *aad_len =3D (uint32_t *)&hash->sha.state1[ > > > ICP_QAT_HW_GALOIS_128_STATE1_SZ + > > - ICP_QAT_HW_GALOIS_H_SZ]) =3D > > - rte_bswap32(add_auth_data_length); > > + ICP_QAT_HW_GALOIS_H_SZ]; > > + > > + *aad_len =3D rte_bswap32(add_auth_data_length); > > + > > proto =3D ICP_QAT_FW_LA_GCM_PROTO; > > } else if (cdesc->qat_hash_alg =3D=3D > ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2) { > > proto =3D ICP_QAT_FW_LA_SNOW_3G_PROTO; > > >=20