From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by dpdk.org (Postfix) with ESMTP id 0CAB18E6D for ; Sat, 17 Sep 2016 01:13:54 +0200 (CEST) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga104.jf.intel.com with ESMTP; 16 Sep 2016 16:13:53 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.30,347,1470726000"; d="scan'208";a="1041532093" Received: from irsmsx107.ger.corp.intel.com ([163.33.3.99]) by fmsmga001.fm.intel.com with ESMTP; 16 Sep 2016 16:13:53 -0700 Received: from irsmsx108.ger.corp.intel.com ([169.254.11.167]) by IRSMSX107.ger.corp.intel.com ([169.254.10.221]) with mapi id 14.03.0248.002; Sat, 17 Sep 2016 00:13:52 +0100 From: "De Lara Guarch, Pablo" To: "Jain, Deepak K" , "dev@dpdk.org" Thread-Topic: [PATCH v3 2/3] crypto/qat: add Kasumi support in Intel(R) QAT driver Thread-Index: AQHSDzh1CH/88JhCPEmKGTImuaKv9aB8sDug Date: Fri, 16 Sep 2016 23:13:51 +0000 Message-ID: References: <1472131419-89617-1-git-send-email-deepak.k.jain@intel.com> <1473933815-185834-1-git-send-email-deepak.k.jain@intel.com> <1473933815-185834-3-git-send-email-deepak.k.jain@intel.com> In-Reply-To: <1473933815-185834-3-git-send-email-deepak.k.jain@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiNjgxZWY3YmMtOTg1NC00NGJiLWIyNTktZWU2ZTk3NzhmMzBhIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX0lDIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE1LjkuNi42IiwiVHJ1c3RlZExhYmVsSGFzaCI6IitPUkNXTUM0SFBCaHJwR0tMNm12dEFCZ0pxZVwvOTdxZTZ3WjN6aDFxWFEwPSJ9 x-ctpclassification: CTP_IC x-originating-ip: [163.33.239.182] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v3 2/3] crypto/qat: add Kasumi support in Intel(R) QAT driver X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 16 Sep 2016 23:13:55 -0000 Hi Deepak, > -----Original Message----- > From: Jain, Deepak K > Sent: Thursday, September 15, 2016 3:04 AM > To: dev@dpdk.org > Cc: De Lara Guarch, Pablo; Jain, Deepak K > Subject: [PATCH v3 2/3] crypto/qat: add Kasumi support in Intel(R) QAT > driver >=20 > This patch add kasumi support in Intel(R) > QuickAssist driver. >=20 > Signed-off-by: Deepak Kumar Jain > --- > doc/guides/cryptodevs/qat.rst | 10 +-- > doc/guides/rel_notes/release_16_11.rst | 2 +- > drivers/crypto/qat/qat_adf/qat_algs.h | 10 ++- > drivers/crypto/qat/qat_adf/qat_algs_build_desc.c | 72 > +++++++++++++++++++-- > drivers/crypto/qat/qat_crypto.c | 79 > ++++++++++++++++++++++-- > 5 files changed, 158 insertions(+), 15 deletions(-) >=20 > diff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rs= t > index 78cadc4..6cdfb93 100644 > --- a/doc/guides/cryptodevs/qat.rst > +++ b/doc/guides/cryptodevs/qat.rst ... > +* Snow3g(UEA2) and Kasumi(F8) supported only if cipher length, cipher > offset fields are byte-aligned. > +* Snow3g(UIA2) and kasumi(F9) supported only if hash length, hash offset > fields are byte-aligned. kasumi -> Kasumi. Actually, it should be KASUMI, and Snow3g should be SNOW = 3G. Will send a patch to fix this in the documentation. > * No BSD support as BSD QAT kernel driver not available. > * Snow3g (UIA2) not supported in the PMD of **Intel QuickAssist > Technology C3xxx** device. >=20 ... > diff --git a/drivers/crypto/qat/qat_crypto.c > b/drivers/crypto/qat/qat_crypto.c > index bc8d5b1..1bb1dd1 100644 > --- a/drivers/crypto/qat/qat_crypto.c > +++ b/drivers/crypto/qat/qat_crypto.c > @@ -387,6 +387,51 @@ static const struct rte_cryptodev_capabilities > qat_pmd_capabilities[] =3D { > }, }, > }, } > }, > + { /* KASUMI (F8) */ > + .op =3D RTE_CRYPTO_OP_TYPE_SYMMETRIC, > + {.sym =3D { > + .xform_type =3D RTE_CRYPTO_SYM_XFORM_CIPHER, > + {.cipher =3D { > + .algo =3D RTE_CRYPTO_CIPHER_KASUMI_F8, > + .block_size =3D 8, > + .key_size =3D { > + .min =3D 16, > + .max =3D 16, > + .increment =3D 0 > + }, > + .iv_size =3D { > + .min =3D 16, > + .max =3D 16, > + .increment =3D 0 > + } IV size is 8. > + }, } > + }, } > + }, > + { /* KASUMI (F9) */ Remove extra tab before brace up here. > + .op =3D RTE_CRYPTO_OP_TYPE_SYMMETRIC, > + {.sym =3D { > + .xform_type =3D RTE_CRYPTO_SYM_XFORM_AUTH, > + {.auth =3D { > + .algo =3D RTE_CRYPTO_AUTH_KASUMI_F9, > + .block_size =3D 8, > + .key_size =3D { > + .min =3D 16, > + .max =3D 16, > + .increment =3D 0 > + }, > + .digest_size =3D { > + .min =3D 4, > + .max =3D 4, > + .increment =3D 0 > + }, > + .aad_size =3D { > + .min =3D 8, > + .max =3D 8, > + .increment =3D 0 > + } > + }, } > + }, } > + }, > RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST() > };