From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by dpdk.org (Postfix) with ESMTP id 0BB9037B8 for ; Fri, 9 Dec 2016 15:02:52 +0100 (CET) Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga103.fm.intel.com with ESMTP; 09 Dec 2016 06:02:51 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.33,324,1477983600"; d="scan'208";a="796144840" Received: from irsmsx102.ger.corp.intel.com ([163.33.3.155]) by FMSMGA003.fm.intel.com with ESMTP; 09 Dec 2016 06:02:51 -0800 Received: from irsmsx104.ger.corp.intel.com ([169.254.5.52]) by IRSMSX102.ger.corp.intel.com ([169.254.2.79]) with mapi id 14.03.0248.002; Fri, 9 Dec 2016 14:02:50 +0000 From: "Sexton, Rory" To: "Wu, Jingjing" CC: "dev@dpdk.org" , "Marjanovic, Nemanja" , "Mcnamara, John" Thread-Topic: [PATCH v1] net/i40e: set no drop for traffic class Thread-Index: AQHSTjYC6DhnQm2wrUeNShG4ogyH+KD5C0CAgAaeg+A= Date: Fri, 9 Dec 2016 14:02:49 +0000 Message-ID: References: <1480859687-27047-1-git-send-email-rory.sexton@intel.com> <9BB6961774997848B5B42BEC655768F80E2C29D0@SHSMSX103.ccr.corp.intel.com> In-Reply-To: <9BB6961774997848B5B42BEC655768F80E2C29D0@SHSMSX103.ccr.corp.intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [163.33.239.180] Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Subject: Re: [dpdk-dev] [PATCH v1] net/i40e: set no drop for traffic class X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 09 Dec 2016 14:02:53 -0000 Hi Jingjing, Yes PRTDCB_TC2PFC is used to control pfc for each TC however we have notice= d other advantages of using the register. By setting the register explicitly by doing the "I40E_WRITE_REG(hw, 0x1c098= 0, 0xff);" it allows for packets to be temporarily stored on the NICs RX SR= AM until there is space for them on SW descriptor ring versus dropping them= when the SW ring becomes full. This also allows for larger burst handling.= It also means SW doesn't have to be as quick to empty the DRAM based descr= iptor rings, allowing more processing on cores. = I have tested using the ETH_DCB_PFC_SUPPORT flag in rte_eth_conf.dcb_capabi= lity_en and rte_eth_dcb_rx_conf.nb_tcs. = This results in the NIC's RX SRAM not being used and if there is no space o= n SW descriptor ring for packet it is dropped. = The advantages of using the PRTDCB_TC2PFC explicitly is that there will be = no packet loss and descriptor rings do not need to be modified (can be left= at 128 for rx and 512 for tx as default settings for apps). Enabling via = this register allows Burst handling to be within the NIC Rx Buffer and SW r= ings combined. = At the moment for tests the rx and tx descriptor rings have to be increased= to 2048 to eliminate packet loss. Ideally it would be an optional setting as using it may increase the max la= tency. Regards, Rory/Nemanja -----Original Message----- From: Wu, Jingjing = Sent: Monday, December 5, 2016 8:45 AM To: Sexton, Rory Cc: dev@dpdk.org; Marjanovic, Nemanja ; Mcnam= ara, John Subject: RE: [PATCH v1] net/i40e: set no drop for traffic class -----Original Message----- From: Sexton, Rory Sent: Sunday, December 4, 2016 9:55 PM To: Wu, Jingjing Cc: dev@dpdk.org; Marjanovic, Nemanja ; Mcnam= ara, John ; Sexton, Rory Subject: [PATCH v1] net/i40e: set no drop for traffic class From: John McNamara The default traffic class in i40e is set to drop versus on ixgbe it isset t= o no drop. This means when packets build up in the RX SRAM on the NIC, they= are dropped, and they do this when the SW descriptor rings fill up. This patch changes this behaviour and our testing shows there are no drops = as a result. Signed-off-by: Rory Sexton Signed-off-by: Nemanja Marjanovic --- drivers/net/i40e/i40e_ethdev.c | 1 + drivers/net/i40e/i40e_rxtx.c | 12 ++++++++++++ drivers/net/i40e/i40e_rxtx.h | 1 + lib/librte_ether/rte_ethdev.h | 24 ++++++++++++++++++++++++ 4 files changed, 38 insertions(+) diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.= c index 67778ba..9702acb 100644 --- a/drivers/net/i40e/i40e_ethdev.c +++ b/drivers/net/i40e/i40e_ethdev.c @@ -553,6 +553,7 @@ static const struct eth_dev_ops i40e_eth_dev_ops =3D { .get_eeprom =3D i40e_get_eeprom, .mac_addr_set =3D i40e_set_default_mac_addr, .mtu_set =3D i40e_dev_mtu_set, + .set_no_drop =3D i40e_set_no_drop, }; = /* store statistics names and its offset in stats structure */ diff --git = a/drivers/net/i40e/i40e_rxtx.c b/drivers/net/i40e/i40e_rxtx.c index 7ae7d9f= ..02aeff4 100644 --- a/drivers/net/i40e/i40e_rxtx.c +++ b/drivers/net/i40e/i40e_rxtx.c @@ -783,6 +783,18 @@ i40e_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pk= ts, uint16_t nb_pkts) return nb_rx; } = +uint32_t +i40e_set_no_drop(struct rte_eth_dev *dev, uint16_t rx_queue_id) { + struct i40e_rx_queue *rxq =3D dev->data->rx_queues[rx_queue_id]; + struct i40e_hw *hw =3D I40E_VSI_TO_HW(rxq->vsi); + + /* Set No Drop Traffic Class. */ + I40E_WRITE_REG(hw, 0x1c0980, 0xff); + + return 1; +} 0x1c0980 is the register (PRTDCB_TC2PFC) which is used to control pfc for e= ach TC. We already have ETH_DCB_PFC_SUPPORT flag in rte_eth_conf.dcb_capability_en = to Control if PFC is enabled. And rte_eth_dcb_rx_conf.nb_tcs identified num= ber of TCs It supports. "I40E_WRITE_REG(hw, 0x1c0980, 0xff);" can be achieved by enabling DCB and P= FC For all TCs. Why do we need such a new API? Thanks Jingjing -------------------------------------------------------------- Intel Research and Development Ireland Limited Registered in Ireland Registered Office: Collinstown Industrial Park, Leixlip, County Kildare Registered Number: 308263 This e-mail and any attachments may contain confidential material for the s= ole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact = the sender and delete all copies.