From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by dpdk.org (Postfix) with ESMTP id E5041FA46 for ; Thu, 19 Jan 2017 11:40:16 +0100 (CET) Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga103.jf.intel.com with ESMTP; 19 Jan 2017 02:40:14 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.33,253,1477983600"; d="scan'208";a="924309409" Received: from irsmsx103.ger.corp.intel.com ([163.33.3.157]) by orsmga003.jf.intel.com with ESMTP; 19 Jan 2017 02:40:14 -0800 Received: from irsmsx156.ger.corp.intel.com (10.108.20.68) by IRSMSX103.ger.corp.intel.com (163.33.3.157) with Microsoft SMTP Server (TLS) id 14.3.248.2; Thu, 19 Jan 2017 10:38:02 +0000 Received: from irsmsx104.ger.corp.intel.com ([169.254.5.142]) by IRSMSX156.ger.corp.intel.com ([169.254.3.104]) with mapi id 14.03.0248.002; Thu, 19 Jan 2017 10:38:01 +0000 From: "Sexton, Rory" To: "Wu, Jingjing" CC: "dev@dpdk.org" , "Marjanovic, Nemanja" Thread-Topic: [PATCH v2] net/i40e: set no drop for traffic class Thread-Index: AQHScBCjkvbcnTsOS06nhdUioE9hwKE8xzOAgAF/oNA= Date: Thu, 19 Jan 2017 10:38:00 +0000 Message-ID: References: <9BB6961774997848B5B42BEC655768F810CBEF56@SHSMSX103.ccr.corp.intel.com> <1484581948-10736-1-git-send-email-rory.sexton@intel.com> <9BB6961774997848B5B42BEC655768F810CCA338@SHSMSX103.ccr.corp.intel.com> In-Reply-To: <9BB6961774997848B5B42BEC655768F810CCA338@SHSMSX103.ccr.corp.intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [163.33.239.182] Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Subject: Re: [dpdk-dev] [PATCH v2] net/i40e: set no drop for traffic class X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2017 10:40:17 -0000 Perhaps the best solution is as suggested to set rte_eth_conf.dcb_capability_en =3D ETH_DCB_PFC_SUPPORT rte_eth_conf.rxmode.mq_mode =3D ETH_MQ_RX_DCB_FLAG and set rte_eth_dcb_rx_conf.nb_tcs to the number of tc's to apply Using this port configuration will give the same behavior of the patch and = it removes the need for an API change. Rory -----Original Message----- From: Wu, Jingjing = Sent: Tuesday, January 17, 2017 3:09 PM To: Sexton, Rory Cc: dev@dpdk.org; Marjanovic, Nemanja Subject: RE: [PATCH v2] net/i40e: set no drop for traffic class > -----Original Message----- > From: Sexton, Rory > Sent: Monday, January 16, 2017 11:52 PM > To: Wu, Jingjing > Cc: dev@dpdk.org; Sexton, Rory ; Marjanovic, = > Nemanja > Subject: [PATCH v2] net/i40e: set no drop for traffic class > = > From: Rory Sexton > = > The default traffic class in i40e is set to drop versus on ixgbe it = > isset to no drop. This means when packets build up in the RX SRAM on = > the NIC, they are dropped, and they do this when the SW descriptor rings = fill up. > = > This patch changes this behaviour and our testing shows there are no = > drops as a result. > = > Signed-off-by: Rory Sexton > Signed-off-by: Nemanja Marjanovic > --- > v2: > * Changed to use existing api to set priority register directly. > = > drivers/net/i40e/i40e_ethdev.c | 3 +++ > 1 file changed, 3 insertions(+) > = > diff --git a/drivers/net/i40e/i40e_ethdev.c = > b/drivers/net/i40e/i40e_ethdev.c index 67778ba..97339b5 100644 > --- a/drivers/net/i40e/i40e_ethdev.c > +++ b/drivers/net/i40e/i40e_ethdev.c > @@ -2985,8 +2985,11 @@ static int > i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev, > __rte_unused struct rte_eth_pfc_conf *pfc_conf) { > + struct i40e_hw *hw =3D I40E_DEV_PRIVATE_TO_HW(dev->data- > >dev_private); > + > PMD_INIT_FUNC_TRACE(); > = > + I40E_WRITE_REG(hw, I40E_PRTDCB_TC2PFC, 0xff); PRTDCB_TC2PFC is the Bitmap who controls the use of Priority Flow Control = (PFC) per each TC. Bit n set to 1b indicates TC n uses PFC in Rx and Tx. Th= e TC is referred as a no-drop TC. And if look the rte_eth_pfc_conf, there is a field called priority, which w= ould map to a TC. Currently, the TC and priority is 1:1 map when dcb is enabled. So how about change it like: Check dcb info, and map the priority to tc, then val =3D 0x1 << tc; I40E_WR= ITE_REG(hw, I40E_PRTDCB_TC2PFC, val); Thanks Jingjing > return -ENOSYS; > } > = > -- > 2.4.3 -------------------------------------------------------------- Intel Research and Development Ireland Limited Registered in Ireland Registered Office: Collinstown Industrial Park, Leixlip, County Kildare Registered Number: 308263 This e-mail and any attachments may contain confidential material for the s= ole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact = the sender and delete all copies.