From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 19379A0524; Thu, 2 Jul 2020 10:09:47 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id E23B31D678; Thu, 2 Jul 2020 10:09:46 +0200 (CEST) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by dpdk.org (Postfix) with ESMTP id 37B0F1D675; Thu, 2 Jul 2020 10:09:45 +0200 (CEST) IronPort-SDR: JA5bHb+OKghFLOUmwMEoPlf6Mku1JHnFUWwfdwqRkdBYDeZP9ZMRFQQwK20n6C0sXM2jQlmAkT 8pVgB/9uO07Q== X-IronPort-AV: E=McAfee;i="6000,8403,9669"; a="144982263" X-IronPort-AV: E=Sophos;i="5.75,303,1589266800"; d="scan'208";a="144982263" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Jul 2020 01:09:44 -0700 IronPort-SDR: JpWWGrNVAPROQ6004O2pL0XvXTA+KZ5nb8R2gWZI3CVO8GT1j+GiMCbvUZgT4MIvh60hd008b7 I02jfFNlhYkg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.75,303,1589266800"; d="scan'208";a="321461879" Received: from fmsmsx107.amr.corp.intel.com ([10.18.124.205]) by FMSMGA003.fm.intel.com with ESMTP; 02 Jul 2020 01:09:44 -0700 Received: from FMSMSX109.amr.corp.intel.com (10.18.116.9) by fmsmsx107.amr.corp.intel.com (10.18.124.205) with Microsoft SMTP Server (TLS) id 14.3.439.0; Thu, 2 Jul 2020 01:06:41 -0700 Received: from cdsmsx152.ccr.corp.intel.com (172.17.4.41) by fmsmsx109.amr.corp.intel.com (10.18.116.9) with Microsoft SMTP Server (TLS) id 14.3.439.0; Thu, 2 Jul 2020 01:06:41 -0700 Received: from cdsmsx102.ccr.corp.intel.com ([169.254.2.8]) by CDSMSX152.ccr.corp.intel.com ([169.254.6.133]) with mapi id 14.03.0439.000; Thu, 2 Jul 2020 16:06:36 +0800 From: "Zhou, JunX W" To: "Xu, Ting" , "dev@dpdk.org" CC: "Dumitrescu, Cristian" , "stable@dpdk.org" Thread-Topic: [dpdk-dev] [PATCH v2] lib/table: fix cache alignment issue Thread-Index: AQHWRGpc+UOS+ZgD70anH4qWkck236j0Blig Date: Thu, 2 Jul 2020 08:06:35 +0000 Message-ID: References: <20200616162705.83575-1-ting.xu@intel.com> <20200617054355.7895-1-ting.xu@intel.com> In-Reply-To: <20200617054355.7895-1-ting.xu@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [172.17.6.105] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v2] lib/table: fix cache alignment issue X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Tested-by: junx.w.zhou@intel.com -----Original Message----- From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Ting Xu Sent: Wednesday, June 17, 2020 1:44 PM To: dev@dpdk.org Cc: Dumitrescu, Cristian ; stable@dpdk.org Subject: [dpdk-dev] [PATCH v2] lib/table: fix cache alignment issue When create softnic hash table with 16 keys, it failed on 32bit environment= because of the structure rte_bucket_4_16 alignment issue. Add __rte_cache_= aligned to ensure correct cache align. Fixes: 8aa327214c ("table: hash") Cc: stable@dpdk.org Signed-off-by: Ting Xu --- v1->v2: Correct patch time --- lib/librte_table/rte_table_hash_key16.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/librte_table/rte_table_hash_key16.c b/lib/librte_table/rte= _table_hash_key16.c index 2cca1c924..5e1665c15 100644 --- a/lib/librte_table/rte_table_hash_key16.c +++ b/lib/librte_table/rte_table_hash_key16.c @@ -44,7 +44,7 @@ struct rte_bucket_4_16 { uint64_t key[4][2]; =20 /* Cache line 2 */ - uint8_t data[0]; + uint8_t data[0] __rte_cache_aligned; }; =20 struct rte_table_hash { -- 2.17.1