From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by dpdk.org (Postfix) with ESMTP id 82028C330 for ; Thu, 28 Jan 2016 08:03:21 +0100 (CET) Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga102.fm.intel.com with ESMTP; 27 Jan 2016 23:03:20 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.22,357,1449561600"; d="scan'208";a="735616566" Received: from fmsmsx108.amr.corp.intel.com ([10.18.124.206]) by orsmga003.jf.intel.com with ESMTP; 27 Jan 2016 23:03:22 -0800 Received: from fmsmsx122.amr.corp.intel.com (10.18.125.37) by FMSMSX108.amr.corp.intel.com (10.18.124.206) with Microsoft SMTP Server (TLS) id 14.3.248.2; Wed, 27 Jan 2016 23:03:19 -0800 Received: from shsmsx101.ccr.corp.intel.com (10.239.4.153) by fmsmsx122.amr.corp.intel.com (10.18.125.37) with Microsoft SMTP Server (TLS) id 14.3.248.2; Wed, 27 Jan 2016 23:03:19 -0800 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.172]) by SHSMSX101.ccr.corp.intel.com ([169.254.1.215]) with mapi id 14.03.0248.002; Thu, 28 Jan 2016 15:03:17 +0800 From: "Tao, Zhe" To: "Wu, Jingjing" Thread-Topic: [dpdk-dev] [PATCH v2 2/2] i40evf: support interrupt based pf reset request Thread-Index: AQHRWKUWew2AD+IQP0GG4F2xeMpB6Z8QgdOg Date: Thu, 28 Jan 2016 07:03:17 +0000 Message-ID: References: <1452688307-20213-1-git-send-email-jingjing.wu@intel.com> <1453859378-23912-1-git-send-email-jingjing.wu@intel.com> <1453859378-23912-3-git-send-email-jingjing.wu@intel.com> In-Reply-To: <1453859378-23912-3-git-send-email-jingjing.wu@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Cc: "dev@dpdk.org" Subject: Re: [dpdk-dev] [PATCH v2 2/2] i40evf: support interrupt based pf reset request X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Jan 2016 07:03:21 -0000 > -----Original Message----- > From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Jingjing Wu > Sent: Wednesday, January 27, 2016 9:50 AM > To: dev@dpdk.org > Subject: [dpdk-dev] [PATCH v2 2/2] i40evf: support interrupt based pf res= et > request >=20 > Interrupt based request of PF reset from PF is supported by enabling the > adminq event process in VF driver. > Users can register a callback for this interrupt event to get informed, w= hen a > PF reset request detected like: > rte_eth_dev_callback_register(portid, > RTE_ETH_EVENT_INTR_RESET, > reset_event_callback, > arg); >=20 > Signed-off-by: Jingjing Wu > --- > doc/guides/rel_notes/release_2_3.rst | 1 + > drivers/net/i40e/i40e_ethdev_vf.c | 274 > +++++++++++++++++++++++++++++++---- > lib/librte_ether/rte_ethdev.h | 1 + > 3 files changed, 246 insertions(+), 30 deletions(-) >=20 > diff --git a/doc/guides/rel_notes/release_2_3.rst > b/doc/guides/rel_notes/release_2_3.rst > index 99de186..73d5f76 100644 > --- a/doc/guides/rel_notes/release_2_3.rst > +++ b/doc/guides/rel_notes/release_2_3.rst > @@ -4,6 +4,7 @@ DPDK Release 2.3 > New Features > ------------ >=20 > +* **Added pf reset event reported in i40e vf PMD driver. >=20 > Resolved Issues > --------------- > diff --git a/drivers/net/i40e/i40e_ethdev_vf.c > b/drivers/net/i40e/i40e_ethdev_vf.c > index 64e6957..1ffe64e 100644 > --- a/drivers/net/i40e/i40e_ethdev_vf.c > +++ b/drivers/net/i40e/i40e_ethdev_vf.c > @@ -74,8 +74,6 @@ > +static void > @@ -1662,7 +1869,8 @@ i40evf_enable_queues_intr(struct rte_eth_dev > *dev) > I40E_WRITE_REG(hw, > I40E_VFINT_DYN_CTL01, > I40E_VFINT_DYN_CTL01_INTENA_MASK | > - I40E_VFINT_DYN_CTL01_CLEARPBA_MASK); > + I40E_VFINT_DYN_CTL01_CLEARPBA_MASK | > + I40E_VFINT_DYN_CTL01_ITR_INDX_MASK); What the usage for ITR bits here? > I40EVF_WRITE_FLUSH(hw); > return; > } > @@ -1673,11 +1881,10 @@ i40evf_enable_queues_intr(struct rte_eth_dev > *dev) >=20 > I40E_VFINT_DYN_CTLN1(I40EVF_VSI_DEFAULT_MSIX_INTR - 1), > I40E_VFINT_DYN_CTLN1_INTENA_MASK | > I40E_VFINT_DYN_CTLN_CLEARPBA_MASK); > - else > - /* To support Linux PF host */ > - I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01, >=20 > -- > 2.4.0