From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by dpdk.org (Postfix) with ESMTP id 46BDBC59C for ; Fri, 29 Jan 2016 09:50:47 +0100 (CET) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga103.jf.intel.com with ESMTP; 29 Jan 2016 00:50:46 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.22,363,1449561600"; d="scan'208";a="900811506" Received: from fmsmsx105.amr.corp.intel.com ([10.18.124.203]) by orsmga002.jf.intel.com with ESMTP; 29 Jan 2016 00:50:46 -0800 Received: from FMSMSX110.amr.corp.intel.com (10.18.116.10) by FMSMSX105.amr.corp.intel.com (10.18.124.203) with Microsoft SMTP Server (TLS) id 14.3.248.2; Fri, 29 Jan 2016 00:50:45 -0800 Received: from shsmsx151.ccr.corp.intel.com (10.239.6.50) by fmsmsx110.amr.corp.intel.com (10.18.116.10) with Microsoft SMTP Server (TLS) id 14.3.248.2; Fri, 29 Jan 2016 00:50:45 -0800 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.172]) by SHSMSX151.ccr.corp.intel.com ([169.254.3.231]) with mapi id 14.03.0248.002; Fri, 29 Jan 2016 16:50:43 +0800 From: "Tao, Zhe" To: "Wu, Jingjing" , "dev@dpdk.org" Thread-Topic: [dpdk-dev] [PATCH v2 2/2] i40evf: support interrupt based pf reset request Thread-Index: AQHRWKUWew2AD+IQP0GG4F2xeMpB6Z8SG5Uw Date: Fri, 29 Jan 2016 08:50:42 +0000 Message-ID: References: <1452688307-20213-1-git-send-email-jingjing.wu@intel.com> <1453859378-23912-1-git-send-email-jingjing.wu@intel.com> <1453859378-23912-3-git-send-email-jingjing.wu@intel.com> In-Reply-To: <1453859378-23912-3-git-send-email-jingjing.wu@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v2 2/2] i40evf: support interrupt based pf reset request X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 29 Jan 2016 08:50:47 -0000 > -----Original Message----- > From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Jingjing Wu > Sent: Wednesday, January 27, 2016 9:50 AM > To: dev@dpdk.org > Subject: [dpdk-dev] [PATCH v2 2/2] i40evf: support interrupt based pf res= et > request >=20 > Interrupt based request of PF reset from PF is supported by enabling the > adminq event process in VF driver. > Users can register a callback for this interrupt event to get informed, w= hen a > PF reset request detected like: > rte_eth_dev_callback_register(portid, > RTE_ETH_EVENT_INTR_RESET, > reset_event_callback, > arg); >=20 > Signed-off-by: Jingjing Wu Two questions, 1.If the VF RX/TX using msix 1 and Admin Queue using msix 0,=20 how the two interrupts can both be read in user spaces, in VM VFIO not supp= orted, 2.But if we want to run l3fwd-power in VF, we can only assign the rx/tx in= tr to msix0, but both thread will using epoll to wait the msix0 event,=20 and intr thread may miss the vf reset event if l3fwd-power thread clean the= msix0 related fd firstly if there are no more packets and msg response come in, the intr thread wil= l not be wake up again