From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by dpdk.org (Postfix) with ESMTP id 759DF5686 for ; Thu, 8 Jan 2015 03:49:46 +0100 (CET) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga103.fm.intel.com with ESMTP; 07 Jan 2015 18:44:56 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.07,719,1413270000"; d="scan'208";a="634106661" Received: from pgsmsx106.gar.corp.intel.com ([10.221.44.98]) by orsmga001.jf.intel.com with ESMTP; 07 Jan 2015 18:49:44 -0800 Received: from shsmsx101.ccr.corp.intel.com (10.239.4.153) by PGSMSX106.gar.corp.intel.com (10.221.44.98) with Microsoft SMTP Server (TLS) id 14.3.195.1; Thu, 8 Jan 2015 10:49:41 +0800 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.182]) by SHSMSX101.ccr.corp.intel.com ([169.254.1.110]) with mapi id 14.03.0195.001; Thu, 8 Jan 2015 10:49:39 +0800 From: "Zhang, Helin" To: "Wu, Jingjing" , "dev@dpdk.org" Thread-Topic: [PATCH v3] i40e: workaround for X710 performance issues Thread-Index: AQHQGQmhQA9VD5m2XkOcLyxX2rZjnpy1p0AwgAABWXA= Date: Thu, 8 Jan 2015 02:49:39 +0000 Message-ID: References: <1418630187-28917-1-git-send-email-helin.zhang@intel.com> <1418718200-31924-1-git-send-email-helin.zhang@intel.com> <9BB6961774997848B5B42BEC655768F8B6DD36@SHSMSX104.ccr.corp.intel.com> In-Reply-To: <9BB6961774997848B5B42BEC655768F8B6DD36@SHSMSX104.ccr.corp.intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Cc: "Rowden, Aaron F" Subject: Re: [dpdk-dev] [PATCH v3] i40e: workaround for X710 performance issues X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 08 Jan 2015 02:49:47 -0000 > -----Original Message----- > From: Wu, Jingjing > Sent: Thursday, January 8, 2015 10:44 AM > To: Zhang, Helin; dev@dpdk.org > Cc: Chen, Jing D; Liu, Jijiang; Cao, Waterman; Lu, Patrick; Rowden, Aaron= F > Subject: RE: [PATCH v3] i40e: workaround for X710 performance issues >=20 >=20 >=20 > > -----Original Message----- > > From: Zhang, Helin > > Sent: Tuesday, December 16, 2014 4:23 PM > > To: dev@dpdk.org > > Cc: Chen, Jing D; Wu, Jingjing; Liu, Jijiang; Cao, Waterman; Lu, > > Patrick; Rowden, Aaron F; Zhang, Helin > > Subject: [PATCH v3] i40e: workaround for X710 performance issues > > > > On X710, performance number is far from the expectation on recent > > firmware versions. The fix for this issue may not be integrated in the > > following firmware version. So the workaround in software driver is nee= ded. > > It needs to modify the initial values of 3 internal only registers. > > Note that the workaround can be removed when it is fixed in firmware in= the > future. > > > > Signed-off-by: Helin Zhang > > --- > > lib/librte_pmd_i40e/i40e_ethdev.c | 89 > > +++++++++++++++++++++++++++++++++++++++ > > 1 file changed, 89 insertions(+) > > > > v2 changes: > > * Added a compile error fix. > > > > v3 changes: > > * Used PRIx32 and PRIx64 instead for printing uint32_t and uint64_t > > variables. > > * Re-worded annotations, and commit logs. > > > > diff --git a/lib/librte_pmd_i40e/i40e_ethdev.c > > b/lib/librte_pmd_i40e/i40e_ethdev.c > > index 008d62c..624f0ce 100644 > > --- a/lib/librte_pmd_i40e/i40e_ethdev.c > > +++ b/lib/librte_pmd_i40e/i40e_ethdev.c > > @@ -198,6 +198,7 @@ static int i40e_dev_filter_ctrl(struct rte_eth_dev > *dev, > > enum rte_filter_type filter_type, > > enum rte_filter_op filter_op, > > void *arg); > > +static void i40e_configure_registers(struct i40e_hw *hw); > > > > /* Default hash key buffer for RSS */ static uint32_t > > rss_key_default[I40E_PFQF_HKEY_MAX_INDEX + 1]; @@ - > > 443,6 +444,16 @@ eth_i40e_dev_init(__rte_unused struct eth_driver > > *eth_drv, > > /* Clear PXE mode */ > > i40e_clear_pxe_mode(hw); > > > > + /* > > + * On X710, performance number is far from the expectation on > > recent > > + * firmware versions. The fix for this issue may not be integrated in > > + * the following firmware version. So the workaround in software > > driver > > + * is needed. It needs to modify the initial values of 3 internal onl= y > > + * registers. Note that the workaround can be removed when it is > > fixed > > + * in firmware in the future. > > + */ > > + i40e_configure_registers(hw); > > + > > /* Get hw capabilities */ > > ret =3D i40e_get_cap(hw); > > if (ret !=3D I40E_SUCCESS) { > > @@ -5294,3 +5305,81 @@ i40e_pctype_to_flowtype(enum > i40e_filter_pctype > > pctype) > > > > return flowtype_table[pctype]; > > } > > + > > +static int > > +i40e_debug_read_register(struct i40e_hw *hw, uint32_t addr, uint64_t > > +*val) { > > + struct i40e_aq_desc desc; > > + struct i40e_aqc_debug_reg_read_write *cmd =3D > > + (struct i40e_aqc_debug_reg_read_write > > *)&desc.params.raw; > > + enum i40e_status_code status; > > + > > + i40e_fill_default_direct_cmd_desc(&desc, > > i40e_aqc_opc_debug_read_reg); > > + cmd->address =3D rte_cpu_to_le_32(addr); > > + status =3D i40e_asq_send_command(hw, &desc, NULL, 0, NULL); > > + if (status < 0) > > + return status; > > + > > + *val =3D ((uint64_t)(rte_le_to_cpu_32(cmd->value_high)) << > > (CHAR_BIT * > > + sizeof(uint32_t))) + rte_le_to_cpu_32(cmd- > > >value_low); > > + >=20 > Do we need to add rte_le_to_cpu_64 here? No, we don't need one more conversion, as 32 bits value are already 'cpu' b= yte order. Thanks, Helin >=20 > > + return status; > > +} > > + > > +/* > > + * On X710, performance number is far from the expectation on recent > > +firmware > > + * versions. The fix for this issue may not be integrated in the > > +following > > + * firmware version. So the workaround in software driver is needed. > > +It needs > > + * to modify the initial values of 3 internal only registers. Note > > +that the > > + * workaround can be removed when it is fixed in firmware in the futur= e. > > + */ > > +static void > > +i40e_configure_registers(struct i40e_hw *hw) { > > +#define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00 > > +#define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08 > > +#define I40E_GL_SWR_PM_UP_THR 0x269FBC > > +#define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200 #define > > +I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200 > > +#define I40E_GL_SWR_PM_UP_THR_VALUE 0x03030303 > > + > > + static const struct { > > + uint32_t addr; > > + uint64_t val; > > + } reg_table[] =3D { > > + {I40E_GL_SWR_PRI_JOIN_MAP_0, > > I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE}, > > + {I40E_GL_SWR_PRI_JOIN_MAP_2, > > I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE}, > > + {I40E_GL_SWR_PM_UP_THR, > > I40E_GL_SWR_PM_UP_THR_VALUE}, > > + }; > > + uint64_t reg; > > + uint32_t i; > > + int ret; > > + > > + /* Below fix is for X710 only */ > > + if (i40e_is_40G_device(hw->device_id)) > > + return; > > + > > + for (i =3D 0; i < RTE_DIM(reg_table); i++) { > > + ret =3D i40e_debug_read_register(hw, reg_table[i].addr, ®); > > + if (ret < 0) { > > + PMD_DRV_LOG(ERR, "Failed to read from > > 0x%"PRIx32, > > + reg_table[i].addr); > > + break; > > + } > > + PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": > > 0x%"PRIx64, > > + reg_table[i].addr, reg); > > + if (reg =3D=3D reg_table[i].val) > > + continue; > > + > > + ret =3D i40e_aq_debug_write_register(hw, reg_table[i].addr, > > + reg_table[i].val, NULL); > > + if (ret < 0) { > > + PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to > > the " > > + "address of 0x%"PRIx32, reg_table[i].val, > > + reg_table[i].addr); > > + break; > > + } > > + PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address > > of " > > + "0x%"PRIx32, reg_table[i].val, reg_table[i].addr); > > + } > > +} > > -- > > 1.8.1.4