Re: [dpdk-dev] [PATCH] kni/ethtool/ixgbe: enforce access between ixgbe PCI and CPU

["Zhang, Helin" <helin.zhang@intel.com>]

Hi Xuelin

> -----Original Message-----
> From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of
> xuelin.shi@freescale.com
> Sent: Wednesday, February 11, 2015 2:50 PM
> To: thomas.monjalon@6wind.com
> Cc: dev@dpdk.org
> Subject: [dpdk-dev] [PATCH] kni/ethtool/ixgbe: enforce access between ixgbe
> PCI and CPU
> 
> From: Xuelin Shi <xuelin.shi@freescale.com>
> 
> make sure:
> 	CPU read from ixgbe with IXGBE_LE32_TO_CPUS
>         CPU write to ixgbe with IXGBE_CPU_TO_LE32
> 
> otherwise, there is endian issue for ixgbe on BIG_ENDIAN CPU.
I got your concern, but you modified in wrong places. Source files in linux/kni/ will
be compiled into a kernel module. So the endian issue will be handled quite well by kernel
functions like writel, readl, etc. And your modifications are not needed at all for KNI
kernel module.

But I think the similar changes are needed in librte_pmd_e1000, librte_pmd_ixgbe,
librte_pmd_i40e, etc.

Regards,
Helin

> 
> Signed-off-by: Xuelin Shi <xuelin.shi@freescale.com>
> ---
>  .../linuxapp/kni/ethtool/ixgbe/ixgbe_osdep.h       | 24
> ++++++++++++++++------
>  1 file changed, 18 insertions(+), 6 deletions(-)
> 
> diff --git a/lib/librte_eal/linuxapp/kni/ethtool/ixgbe/ixgbe_osdep.h
> b/lib/librte_eal/linuxapp/kni/ethtool/ixgbe/ixgbe_osdep.h
> index d161600..0612632 100644
> --- a/lib/librte_eal/linuxapp/kni/ethtool/ixgbe/ixgbe_osdep.h
> +++ b/lib/librte_eal/linuxapp/kni/ethtool/ixgbe/ixgbe_osdep.h
> @@ -53,6 +53,16 @@
> 
>  #undef ASSERT
> 
> +static inline uint32_t ixgbe_read_addr(volatile void* addr) {
> +	return IXGBE_LE32_TO_CPUS(*((volatile uint32_t *)addr)); }
> +
> +static inline uint32_t ixgbe_write_addr(u32 value, volatile void* addr)
> +{
> +	return writel(IXGBE_CPU_TO_LE32(value), addr); }
> +
>  #ifdef DBG
>  #define hw_dbg(hw, S, A...)	printk(KERN_DEBUG S, ## A)
>  #else
> @@ -91,19 +101,20 @@
>  	default: \
>  		break; \
>  	} \
> -	writel((value), ((a)->hw_addr + (reg))); \
> +	ixgbe_write_addr((value), ((a)->hw_addr + (reg))); \
>  } while (0)
>  #else
> -#define IXGBE_WRITE_REG(a, reg, value) writel((value), ((a)->hw_addr +
> (reg)))
> +#define IXGBE_WRITE_REG(a, reg, value) \
> +	ixgbe_write_addr((value), ((a)->hw_addr + (reg)))
>  #endif
> 
> -#define IXGBE_READ_REG(a, reg) readl((a)->hw_addr + (reg))
> +#define IXGBE_READ_REG(a, reg) ixgbe_read_addr((a)->hw_addr + (reg))
> 
>  #define IXGBE_WRITE_REG_ARRAY(a, reg, offset, value) ( \
> -	writel((value), ((a)->hw_addr + (reg) + ((offset) << 2))))
> +	ixgbe_write_addr((value), ((a)->hw_addr + (reg) + ((offset) << 2))))
> 
>  #define IXGBE_READ_REG_ARRAY(a, reg, offset) ( \
> -	readl((a)->hw_addr + (reg) + ((offset) << 2)))
> +	ixgbe_read_addr((a)->hw_addr + (reg) + ((offset) << 2)))
> 
>  #ifndef writeq
>  #define writeq(val, addr)	do { writel((u32) (val), addr); \
> @@ -111,7 +122,8 @@
>  				} while (0);
>  #endif
> 
> -#define IXGBE_WRITE_REG64(a, reg, value) writeq((value), ((a)->hw_addr +
> (reg)))
> +#define IXGBE_WRITE_REG64(a, reg, value) \
> +	writeq((cpu_to_le64(value)), ((a)->hw_addr + (reg)))
> 
>  #define IXGBE_WRITE_FLUSH(a) IXGBE_READ_REG(a, IXGBE_STATUS)
> struct ixgbe_hw;
> --
> 1.9.1