From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by dpdk.org (Postfix) with ESMTP id 0C13CB62 for ; Wed, 25 Mar 2015 07:33:28 +0100 (CET) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga101.fm.intel.com with ESMTP; 24 Mar 2015 23:33:28 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.11,463,1422950400"; d="scan'208";a="685245902" Received: from pgsmsx108.gar.corp.intel.com ([10.221.44.103]) by fmsmga001.fm.intel.com with ESMTP; 24 Mar 2015 23:33:28 -0700 Received: from kmsmsx154.gar.corp.intel.com (172.21.73.14) by PGSMSX108.gar.corp.intel.com (10.221.44.103) with Microsoft SMTP Server (TLS) id 14.3.224.2; Wed, 25 Mar 2015 14:33:21 +0800 Received: from shsmsx101.ccr.corp.intel.com (10.239.4.153) by KMSMSX154.gar.corp.intel.com (172.21.73.14) with Microsoft SMTP Server (TLS) id 14.3.224.2; Wed, 25 Mar 2015 14:33:21 +0800 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.149]) by SHSMSX101.ccr.corp.intel.com ([169.254.1.36]) with mapi id 14.03.0224.002; Wed, 25 Mar 2015 14:33:20 +0800 From: "Zhang, Helin" To: "xuelin.shi@freescale.com" , "thomas.monjalon@6wind.com" Thread-Topic: [dpdk-dev] [PATCH] ixgbe: fix ixgbe PCI access endian issue Thread-Index: AQHQRmshSp2WPeFXfkWcpNOwi9584p0s/dkg Date: Wed, 25 Mar 2015 06:33:20 +0000 Message-ID: References: <1423703990-29031-1-git-send-email-xuelin.shi@freescale.com> In-Reply-To: <1423703990-29031-1-git-send-email-xuelin.shi@freescale.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Cc: "dev@dpdk.org" Subject: Re: [dpdk-dev] [PATCH] ixgbe: fix ixgbe PCI access endian issue X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 25 Mar 2015 06:33:29 -0000 > -----Original Message----- > From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of > xuelin.shi@freescale.com > Sent: Thursday, February 12, 2015 9:20 AM > To: thomas.monjalon@6wind.com > Cc: dev@dpdk.org > Subject: [dpdk-dev] [PATCH] ixgbe: fix ixgbe PCI access endian issue >=20 > From: Xuelin Shi >=20 > ixgbe is little endian, but cpu maybe not. > add necessary conversions. > rte_cpu_to_le_32(...) for PCI write > rte_le_to_cpu_32(...) for PCI read. >=20 > Signed-off-by: Xuelin Shi Acked-by: Helin Zhang > --- > lib/librte_pmd_ixgbe/ixgbe/ixgbe_osdep.h | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) >=20 > diff --git a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_osdep.h > b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_osdep.h > index 2d40bfd..f8bfb3f 100644 > --- a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_osdep.h > +++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_osdep.h > @@ -119,11 +119,11 @@ typedef int bool; >=20 > static inline uint32_t ixgbe_read_addr(volatile void* addr) { > - return IXGBE_PCI_REG(addr); > + return rte_le_to_cpu_32(IXGBE_PCI_REG(addr)); > } >=20 > #define IXGBE_PCI_REG_WRITE(reg, value) do { \ > - IXGBE_PCI_REG((reg)) =3D (value); \ > + IXGBE_PCI_REG((reg)) =3D (rte_cpu_to_le_32(value)); \ > } while(0) >=20 > #define IXGBE_PCI_REG_ADDR(hw, reg) \ > -- > 1.9.1