From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by dpdk.org (Postfix) with ESMTP id B452C106A for ; Tue, 17 Jan 2017 02:31:37 +0100 (CET) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga102.jf.intel.com with ESMTP; 16 Jan 2017 17:31:36 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.33,242,1477983600"; d="scan'208";a="31370023" Received: from fmsmsx103.amr.corp.intel.com ([10.18.124.201]) by orsmga002.jf.intel.com with ESMTP; 16 Jan 2017 17:31:34 -0800 Received: from shsmsx151.ccr.corp.intel.com (10.239.6.50) by FMSMSX103.amr.corp.intel.com (10.18.124.201) with Microsoft SMTP Server (TLS) id 14.3.248.2; Mon, 16 Jan 2017 17:31:34 -0800 Received: from shsmsx103.ccr.corp.intel.com ([169.254.4.20]) by SHSMSX151.ccr.corp.intel.com ([169.254.3.204]) with mapi id 14.03.0248.002; Tue, 17 Jan 2017 09:31:30 +0800 From: "Zhang, Helin" To: "Zhang, Qi Z" , "Lu, Wenzhuo" CC: "dev@dpdk.org" Thread-Topic: [PATCH v2] net/ixgbe: fix interrupt block issue Thread-Index: AQHScF3rPgV2AE3yB0y/JHlab251B6E737AQ Date: Tue, 17 Jan 2017 01:31:29 +0000 Message-ID: References: <1484589732-13537-1-git-send-email-qi.z.zhang@intel.com> In-Reply-To: <1484589732-13537-1-git-send-email-qi.z.zhang@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v2] net/ixgbe: fix interrupt block issue X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 17 Jan 2017 01:31:38 -0000 > -----Original Message----- > From: Zhang, Qi Z > Sent: Tuesday, January 17, 2017 2:02 AM > To: Lu, Wenzhuo; Zhang, Helin > Cc: dev@dpdk.org; Zhang, Qi Z > Subject: [PATCH v2] net/ixgbe: fix interrupt block issue >=20 > When handle link status change interrupt, interrupt will be blocked until > delayed handler finish, the duration is at least 1 second, this may cause > following VF to PF mailbox traffic be blocked and sometimes PF can't ack = to > VF in time before VF think it's time out. > This patch remove this limitation, interrupt will be enabled before inter= rupt > handler finish, and a flag is used to prevent re-entering delayed handler= . >=20 > Fixes: 0a45657a6794 ("pci: rework interrupt handling") >=20 > Signed-off-by: Qi Zhang > --- > v2: > - rebase to dpdk-next-net >=20 > drivers/net/ixgbe/ixgbe_ethdev.c | 19 +++++++++---------- > drivers/net/ixgbe/ixgbe_ethdev.h | 2 ++ > 2 files changed, 11 insertions(+), 10 deletions(-) >=20 > diff --git a/drivers/net/ixgbe/ixgbe_ethdev.c > b/drivers/net/ixgbe/ixgbe_ethdev.c > index c66f432..f36ce89 100644 > --- a/drivers/net/ixgbe/ixgbe_ethdev.c > +++ b/drivers/net/ixgbe/ixgbe_ethdev.c > @@ -3762,7 +3762,6 @@ ixgbe_dev_interrupt_action(struct rte_eth_dev > *dev, > IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private); > int64_t timeout; > struct rte_eth_link link; > - int intr_enable_delay =3D false; > struct ixgbe_hw *hw =3D > IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); >=20 > @@ -3778,7 +3777,7 @@ ixgbe_dev_interrupt_action(struct rte_eth_dev > *dev, > intr->flags &=3D ~IXGBE_FLAG_PHY_INTERRUPT; > } >=20 > - if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) { > + if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE && !intr->delay) { > /* get the link status before link update, for predicting later > */ > memset(&link, 0, sizeof(link)); > rte_ixgbe_dev_atomic_read_link_status(dev, &link); @@ - > 3795,20 +3794,16 @@ ixgbe_dev_interrupt_action(struct rte_eth_dev *dev, > timeout =3D IXGBE_LINK_DOWN_CHECK_TIMEOUT; >=20 > ixgbe_dev_link_status_print(dev); > + intr->delay =3D true; >=20 > - intr_enable_delay =3D true; > - } > - > - if (intr_enable_delay) { > if (rte_eal_alarm_set(timeout * 1000, > ixgbe_dev_interrupt_delayed_handler, > (void *)dev) < 0) > PMD_DRV_LOG(ERR, "Error setting alarm"); > - } else { > - PMD_DRV_LOG(DEBUG, "enable intr immediately"); > - ixgbe_enable_intr(dev); > - rte_intr_enable(intr_handle); > } >=20 > + PMD_DRV_LOG(DEBUG, "enable intr immediately"); > + ixgbe_enable_intr(dev); > + rte_intr_enable(intr_handle); I think we should still disable LSC interrupt before the delayed handling, = to avoid any chaos on potential too many interrupts being reported. Of cause other interrupts can be enabled here, to fix the issue you found. Thanks, Helin >=20 > return 0; > } > @@ -3839,6 +3834,8 @@ ixgbe_dev_interrupt_delayed_handler(void > *param) > IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); > uint32_t eicr; >=20 > + ixgbe_disable_intr(hw); > + > eicr =3D IXGBE_READ_REG(hw, IXGBE_EICR); > if (eicr & IXGBE_EICR_MAILBOX) > ixgbe_pf_mbx_process(dev); > @@ -3861,6 +3858,8 @@ ixgbe_dev_interrupt_delayed_handler(void > *param) > intr->flags &=3D ~IXGBE_FLAG_MACSEC; > } >=20 > + intr->delay =3D false; > + > PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", > eicr); > ixgbe_enable_intr(dev); > rte_intr_enable(intr_handle); > diff --git a/drivers/net/ixgbe/ixgbe_ethdev.h > b/drivers/net/ixgbe/ixgbe_ethdev.h > index 6695b68..b931108 100644 > --- a/drivers/net/ixgbe/ixgbe_ethdev.h > +++ b/drivers/net/ixgbe/ixgbe_ethdev.h > @@ -200,6 +200,8 @@ struct ixgbe_hw_fdir_info { struct ixgbe_interrupt { > uint32_t flags; > uint32_t mask; > + /* to prevent re-enter delayed handler */ > + uint8_t delay; Use bool to replace uint8_t? Thanks, Helin > }; >=20 > struct ixgbe_stat_mapping_registers { > -- > 2.7.4