From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by dpdk.org (Postfix) with ESMTP id 8CF0E2C28 for ; Fri, 15 Mar 2019 01:46:54 +0100 (CET) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 14 Mar 2019 17:46:53 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.58,480,1544515200"; d="scan'208";a="142175774" Received: from fmsmsx103.amr.corp.intel.com ([10.18.124.201]) by orsmga002.jf.intel.com with ESMTP; 14 Mar 2019 17:46:52 -0700 Received: from fmsmsx124.amr.corp.intel.com (10.18.125.39) by FMSMSX103.amr.corp.intel.com (10.18.124.201) with Microsoft SMTP Server (TLS) id 14.3.408.0; Thu, 14 Mar 2019 17:46:52 -0700 Received: from shsmsx105.ccr.corp.intel.com (10.239.4.158) by fmsmsx124.amr.corp.intel.com (10.18.125.39) with Microsoft SMTP Server (TLS) id 14.3.408.0; Thu, 14 Mar 2019 17:46:52 -0700 Received: from shsmsx101.ccr.corp.intel.com ([169.254.1.158]) by SHSMSX105.ccr.corp.intel.com ([169.254.11.113]) with mapi id 14.03.0415.000; Fri, 15 Mar 2019 08:46:49 +0800 From: "Yang, Qiming" To: "Zhang, Qi Z" , "Lu, Wenzhuo" CC: "dev@dpdk.org" , "Stillwell Jr, Paul M" , "Yigit, Ferruh" Thread-Topic: [PATCH v3 01/38] net/ice/base: add switch resource allocation and free Thread-Index: AQHU19h6a9cshBAleUyrwp4Htsi5W6YL4RdA Date: Fri, 15 Mar 2019 00:46:48 +0000 Message-ID: References: <20190228055650.25237-1-qi.z.zhang@intel.com> <20190311070441.5501-1-qi.z.zhang@intel.com> <20190311070441.5501-2-qi.z.zhang@intel.com> In-Reply-To: <20190311070441.5501-2-qi.z.zhang@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiYWM1M2FiZWItMjBiNS00YWUzLTk3OWMtMTNhMGY1NGJhOTliIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiUTdcL2xIeDFpUmpsVk54c20ra1NMUDdjcWZxVHhjNGd1eUFWUHl1N1c5ZkgwXC9KeW5GclZnMmp2VGdaZUV2UzNvIn0= x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.0.400.15 dlp-reaction: no-action x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v3 01/38] net/ice/base: add switch resource allocation and free X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 15 Mar 2019 00:46:55 -0000 > -----Original Message----- > From: Zhang, Qi Z > Sent: Monday, March 11, 2019 3:04 PM > To: Lu, Wenzhuo ; Yang, Qiming > > Cc: dev@dpdk.org; Stillwell Jr, Paul M ; Y= igit, > Ferruh ; Zhang, Qi Z > Subject: [PATCH v3 01/38] net/ice/base: add switch resource allocation an= d > free >=20 > Add two APIs ice_alloc_sw and ice_free_sw to support switch related > resource allocation and free. >=20 > These APIs is required when we enable switch flow. >=20 Is or are? > Signed-off-by: Paul M Stillwell Jr > Signed-off-by: Qi Zhang > --- > drivers/net/ice/base/ice_switch.c | 150 > ++++++++++++++++++++++++++++++++++++++ > drivers/net/ice/base/ice_switch.h | 5 ++ > 2 files changed, 155 insertions(+) >=20 > diff --git a/drivers/net/ice/base/ice_switch.c > b/drivers/net/ice/base/ice_switch.c > index 0379cd045..a7b712e17 100644 > --- a/drivers/net/ice/base/ice_switch.c > +++ b/drivers/net/ice/base/ice_switch.c > @@ -129,6 +129,156 @@ ice_aq_get_sw_cfg(struct ice_hw *hw, struct > ice_aqc_get_sw_cfg_resp *buf, } >=20 >=20 > +/** > + * ice_alloc_sw - allocate resources specific to switch > + * @hw: pointer to the HW struct > + * @ena_stats: true to turn on VEB stats > + * @shared_res: true for shared resource, false for dedicated resource > + * @sw_id: switch ID returned > + * @counter_id: VEB counter ID returned > + * > + * allocates switch resources (SWID and VEB counter) (0x0208) */ enum > +ice_status ice_alloc_sw(struct ice_hw *hw, bool ena_stats, bool > +shared_res, u16 *sw_id, > + u16 *counter_id) > +{ > + struct ice_aqc_alloc_free_res_elem *sw_buf; > + struct ice_aqc_res_elem *sw_ele; > + enum ice_status status; > + u16 buf_len; > + > + buf_len =3D sizeof(*sw_buf); > + sw_buf =3D (struct ice_aqc_alloc_free_res_elem *) > + ice_malloc(hw, buf_len); > + if (!sw_buf) > + return ICE_ERR_NO_MEMORY; > + > + /* Prepare buffer for switch ID. > + * The number of resource entries in buffer is passed as 1 since only > a > + * single switch/VEB instance is allocated, and hence a single sw_id > + * is requested. > + */ > + sw_buf->num_elems =3D CPU_TO_LE16(1); > + sw_buf->res_type =3D > + CPU_TO_LE16(ICE_AQC_RES_TYPE_SWID | > + (shared_res ? ICE_AQC_RES_TYPE_FLAG_SHARED : > + ICE_AQC_RES_TYPE_FLAG_DEDICATED)); > + > + status =3D ice_aq_alloc_free_res(hw, 1, sw_buf, buf_len, > + ice_aqc_opc_alloc_res, NULL); > + > + if (status) > + goto ice_alloc_sw_exit; > + > + sw_ele =3D &sw_buf->elem[0]; > + *sw_id =3D LE16_TO_CPU(sw_ele->e.sw_resp); > + > + if (ena_stats) { > + /* Prepare buffer for VEB Counter */ > + enum ice_adminq_opc opc =3D ice_aqc_opc_alloc_res; > + struct ice_aqc_alloc_free_res_elem *counter_buf; > + struct ice_aqc_res_elem *counter_ele; > + > + counter_buf =3D (struct ice_aqc_alloc_free_res_elem *) > + ice_malloc(hw, buf_len); > + if (!counter_buf) { > + status =3D ICE_ERR_NO_MEMORY; > + goto ice_alloc_sw_exit; > + } > + > + /* The number of resource entries in buffer is passed as 1 > since > + * only a single switch/VEB instance is allocated, and hence a > + * single VEB counter is requested. > + */ > + counter_buf->num_elems =3D CPU_TO_LE16(1); > + counter_buf->res_type =3D > + CPU_TO_LE16(ICE_AQC_RES_TYPE_VEB_COUNTER | > + ICE_AQC_RES_TYPE_FLAG_DEDICATED); > + status =3D ice_aq_alloc_free_res(hw, 1, counter_buf, buf_len, > + opc, NULL); > + > + if (status) { > + ice_free(hw, counter_buf); > + goto ice_alloc_sw_exit; > + } > + counter_ele =3D &counter_buf->elem[0]; > + *counter_id =3D LE16_TO_CPU(counter_ele->e.sw_resp); > + ice_free(hw, counter_buf); > + } > + > +ice_alloc_sw_exit: > + ice_free(hw, sw_buf); > + return status; > +} > + > +/** > + * ice_free_sw - free resources specific to switch > + * @hw: pointer to the HW struct > + * @sw_id: switch ID returned > + * @counter_id: VEB counter ID returned > + * > + * free switch resources (SWID and VEB counter) (0x0209) > + * > + * NOTE: This function frees multiple resources. It continues > + * releasing other resources even after it encounters error. > + * The error code returned is the last error it encountered. > + */ > +enum ice_status ice_free_sw(struct ice_hw *hw, u16 sw_id, u16 > +counter_id) { > + struct ice_aqc_alloc_free_res_elem *sw_buf, *counter_buf; > + enum ice_status status, ret_status; > + u16 buf_len; > + > + buf_len =3D sizeof(*sw_buf); > + sw_buf =3D (struct ice_aqc_alloc_free_res_elem *) > + ice_malloc(hw, buf_len); > + if (!sw_buf) > + return ICE_ERR_NO_MEMORY; > + > + /* Prepare buffer to free for switch ID res. > + * The number of resource entries in buffer is passed as 1 since only > a > + * single switch/VEB instance is freed, and hence a single sw_id > + * is released. > + */ > + sw_buf->num_elems =3D CPU_TO_LE16(1); > + sw_buf->res_type =3D CPU_TO_LE16(ICE_AQC_RES_TYPE_SWID); > + sw_buf->elem[0].e.sw_resp =3D CPU_TO_LE16(sw_id); > + > + ret_status =3D ice_aq_alloc_free_res(hw, 1, sw_buf, buf_len, > + ice_aqc_opc_free_res, NULL); > + > + if (ret_status) > + ice_debug(hw, ICE_DBG_SW, "CQ CMD Buffer:\n"); > + > + /* Prepare buffer to free for VEB Counter resource */ > + counter_buf =3D (struct ice_aqc_alloc_free_res_elem *) > + ice_malloc(hw, buf_len); > + if (!counter_buf) { > + ice_free(hw, sw_buf); > + return ICE_ERR_NO_MEMORY; > + } > + > + /* The number of resource entries in buffer is passed as 1 since only > a > + * single switch/VEB instance is freed, and hence a single VEB counter > + * is released > + */ > + counter_buf->num_elems =3D CPU_TO_LE16(1); > + counter_buf->res_type =3D > CPU_TO_LE16(ICE_AQC_RES_TYPE_VEB_COUNTER); > + counter_buf->elem[0].e.sw_resp =3D CPU_TO_LE16(counter_id); > + > + status =3D ice_aq_alloc_free_res(hw, 1, counter_buf, buf_len, > + ice_aqc_opc_free_res, NULL); > + if (status) { > + ice_debug(hw, ICE_DBG_SW, > + "VEB counter resource could not be freed\n"); > + ret_status =3D status; > + } > + > + ice_free(hw, counter_buf); > + ice_free(hw, sw_buf); > + return ret_status; > +} >=20 > /** > * ice_aq_add_vsi > diff --git a/drivers/net/ice/base/ice_switch.h > b/drivers/net/ice/base/ice_switch.h > index 66a172fc2..dd21781f7 100644 > --- a/drivers/net/ice/base/ice_switch.h > +++ b/drivers/net/ice/base/ice_switch.h > @@ -290,6 +290,11 @@ ice_free_vlan_res_counter(struct ice_hw *hw, u16 > counter_id); > /* Switch/bridge related commands */ > enum ice_status ice_update_sw_rule_bridge_mode(struct ice_hw *hw); > enum ice_status > +ice_alloc_sw(struct ice_hw *hw, bool ena_stats, bool shared_res, u16 > *sw_id, > + u16 *counter_id); > +enum ice_status > +ice_free_sw(struct ice_hw *hw, u16 sw_id, u16 counter_id); enum > +ice_status > ice_add_vlan(struct ice_hw *hw, struct LIST_HEAD_TYPE *m_list); enum > ice_status ice_add_mac(struct ice_hw *hw, struct LIST_HEAD_TYPE *m_lst); > enum ice_status ice_remove_mac(struct ice_hw *hw, struct LIST_HEAD_TYPE > *m_lst); > -- > 2.13.6 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by dpdk.space (Postfix) with ESMTP id 40053A0096 for ; Fri, 15 Mar 2019 01:46:57 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 46725324D; Fri, 15 Mar 2019 01:46:56 +0100 (CET) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by dpdk.org (Postfix) with ESMTP id 8CF0E2C28 for ; Fri, 15 Mar 2019 01:46:54 +0100 (CET) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 14 Mar 2019 17:46:53 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.58,480,1544515200"; d="scan'208";a="142175774" Received: from fmsmsx103.amr.corp.intel.com ([10.18.124.201]) by orsmga002.jf.intel.com with ESMTP; 14 Mar 2019 17:46:52 -0700 Received: from fmsmsx124.amr.corp.intel.com (10.18.125.39) by FMSMSX103.amr.corp.intel.com (10.18.124.201) with Microsoft SMTP Server (TLS) id 14.3.408.0; Thu, 14 Mar 2019 17:46:52 -0700 Received: from shsmsx105.ccr.corp.intel.com (10.239.4.158) by fmsmsx124.amr.corp.intel.com (10.18.125.39) with Microsoft SMTP Server (TLS) id 14.3.408.0; Thu, 14 Mar 2019 17:46:52 -0700 Received: from shsmsx101.ccr.corp.intel.com ([169.254.1.158]) by SHSMSX105.ccr.corp.intel.com ([169.254.11.113]) with mapi id 14.03.0415.000; Fri, 15 Mar 2019 08:46:49 +0800 From: "Yang, Qiming" To: "Zhang, Qi Z" , "Lu, Wenzhuo" CC: "dev@dpdk.org" , "Stillwell Jr, Paul M" , "Yigit, Ferruh" Thread-Topic: [PATCH v3 01/38] net/ice/base: add switch resource allocation and free Thread-Index: AQHU19h6a9cshBAleUyrwp4Htsi5W6YL4RdA Date: Fri, 15 Mar 2019 00:46:48 +0000 Message-ID: References: <20190228055650.25237-1-qi.z.zhang@intel.com> <20190311070441.5501-1-qi.z.zhang@intel.com> <20190311070441.5501-2-qi.z.zhang@intel.com> In-Reply-To: <20190311070441.5501-2-qi.z.zhang@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiYWM1M2FiZWItMjBiNS00YWUzLTk3OWMtMTNhMGY1NGJhOTliIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiUTdcL2xIeDFpUmpsVk54c20ra1NMUDdjcWZxVHhjNGd1eUFWUHl1N1c5ZkgwXC9KeW5GclZnMmp2VGdaZUV2UzNvIn0= x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.0.400.15 dlp-reaction: no-action x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v3 01/38] net/ice/base: add switch resource allocation and free X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Message-ID: <20190315004648.dzR96LoliNFxk_z16895-_vS509dmhn2Xt_1_jBI2FA@z> > -----Original Message----- > From: Zhang, Qi Z > Sent: Monday, March 11, 2019 3:04 PM > To: Lu, Wenzhuo ; Yang, Qiming > > Cc: dev@dpdk.org; Stillwell Jr, Paul M ; Y= igit, > Ferruh ; Zhang, Qi Z > Subject: [PATCH v3 01/38] net/ice/base: add switch resource allocation an= d > free >=20 > Add two APIs ice_alloc_sw and ice_free_sw to support switch related > resource allocation and free. >=20 > These APIs is required when we enable switch flow. >=20 Is or are? > Signed-off-by: Paul M Stillwell Jr > Signed-off-by: Qi Zhang > --- > drivers/net/ice/base/ice_switch.c | 150 > ++++++++++++++++++++++++++++++++++++++ > drivers/net/ice/base/ice_switch.h | 5 ++ > 2 files changed, 155 insertions(+) >=20 > diff --git a/drivers/net/ice/base/ice_switch.c > b/drivers/net/ice/base/ice_switch.c > index 0379cd045..a7b712e17 100644 > --- a/drivers/net/ice/base/ice_switch.c > +++ b/drivers/net/ice/base/ice_switch.c > @@ -129,6 +129,156 @@ ice_aq_get_sw_cfg(struct ice_hw *hw, struct > ice_aqc_get_sw_cfg_resp *buf, } >=20 >=20 > +/** > + * ice_alloc_sw - allocate resources specific to switch > + * @hw: pointer to the HW struct > + * @ena_stats: true to turn on VEB stats > + * @shared_res: true for shared resource, false for dedicated resource > + * @sw_id: switch ID returned > + * @counter_id: VEB counter ID returned > + * > + * allocates switch resources (SWID and VEB counter) (0x0208) */ enum > +ice_status ice_alloc_sw(struct ice_hw *hw, bool ena_stats, bool > +shared_res, u16 *sw_id, > + u16 *counter_id) > +{ > + struct ice_aqc_alloc_free_res_elem *sw_buf; > + struct ice_aqc_res_elem *sw_ele; > + enum ice_status status; > + u16 buf_len; > + > + buf_len =3D sizeof(*sw_buf); > + sw_buf =3D (struct ice_aqc_alloc_free_res_elem *) > + ice_malloc(hw, buf_len); > + if (!sw_buf) > + return ICE_ERR_NO_MEMORY; > + > + /* Prepare buffer for switch ID. > + * The number of resource entries in buffer is passed as 1 since only > a > + * single switch/VEB instance is allocated, and hence a single sw_id > + * is requested. > + */ > + sw_buf->num_elems =3D CPU_TO_LE16(1); > + sw_buf->res_type =3D > + CPU_TO_LE16(ICE_AQC_RES_TYPE_SWID | > + (shared_res ? ICE_AQC_RES_TYPE_FLAG_SHARED : > + ICE_AQC_RES_TYPE_FLAG_DEDICATED)); > + > + status =3D ice_aq_alloc_free_res(hw, 1, sw_buf, buf_len, > + ice_aqc_opc_alloc_res, NULL); > + > + if (status) > + goto ice_alloc_sw_exit; > + > + sw_ele =3D &sw_buf->elem[0]; > + *sw_id =3D LE16_TO_CPU(sw_ele->e.sw_resp); > + > + if (ena_stats) { > + /* Prepare buffer for VEB Counter */ > + enum ice_adminq_opc opc =3D ice_aqc_opc_alloc_res; > + struct ice_aqc_alloc_free_res_elem *counter_buf; > + struct ice_aqc_res_elem *counter_ele; > + > + counter_buf =3D (struct ice_aqc_alloc_free_res_elem *) > + ice_malloc(hw, buf_len); > + if (!counter_buf) { > + status =3D ICE_ERR_NO_MEMORY; > + goto ice_alloc_sw_exit; > + } > + > + /* The number of resource entries in buffer is passed as 1 > since > + * only a single switch/VEB instance is allocated, and hence a > + * single VEB counter is requested. > + */ > + counter_buf->num_elems =3D CPU_TO_LE16(1); > + counter_buf->res_type =3D > + CPU_TO_LE16(ICE_AQC_RES_TYPE_VEB_COUNTER | > + ICE_AQC_RES_TYPE_FLAG_DEDICATED); > + status =3D ice_aq_alloc_free_res(hw, 1, counter_buf, buf_len, > + opc, NULL); > + > + if (status) { > + ice_free(hw, counter_buf); > + goto ice_alloc_sw_exit; > + } > + counter_ele =3D &counter_buf->elem[0]; > + *counter_id =3D LE16_TO_CPU(counter_ele->e.sw_resp); > + ice_free(hw, counter_buf); > + } > + > +ice_alloc_sw_exit: > + ice_free(hw, sw_buf); > + return status; > +} > + > +/** > + * ice_free_sw - free resources specific to switch > + * @hw: pointer to the HW struct > + * @sw_id: switch ID returned > + * @counter_id: VEB counter ID returned > + * > + * free switch resources (SWID and VEB counter) (0x0209) > + * > + * NOTE: This function frees multiple resources. It continues > + * releasing other resources even after it encounters error. > + * The error code returned is the last error it encountered. > + */ > +enum ice_status ice_free_sw(struct ice_hw *hw, u16 sw_id, u16 > +counter_id) { > + struct ice_aqc_alloc_free_res_elem *sw_buf, *counter_buf; > + enum ice_status status, ret_status; > + u16 buf_len; > + > + buf_len =3D sizeof(*sw_buf); > + sw_buf =3D (struct ice_aqc_alloc_free_res_elem *) > + ice_malloc(hw, buf_len); > + if (!sw_buf) > + return ICE_ERR_NO_MEMORY; > + > + /* Prepare buffer to free for switch ID res. > + * The number of resource entries in buffer is passed as 1 since only > a > + * single switch/VEB instance is freed, and hence a single sw_id > + * is released. > + */ > + sw_buf->num_elems =3D CPU_TO_LE16(1); > + sw_buf->res_type =3D CPU_TO_LE16(ICE_AQC_RES_TYPE_SWID); > + sw_buf->elem[0].e.sw_resp =3D CPU_TO_LE16(sw_id); > + > + ret_status =3D ice_aq_alloc_free_res(hw, 1, sw_buf, buf_len, > + ice_aqc_opc_free_res, NULL); > + > + if (ret_status) > + ice_debug(hw, ICE_DBG_SW, "CQ CMD Buffer:\n"); > + > + /* Prepare buffer to free for VEB Counter resource */ > + counter_buf =3D (struct ice_aqc_alloc_free_res_elem *) > + ice_malloc(hw, buf_len); > + if (!counter_buf) { > + ice_free(hw, sw_buf); > + return ICE_ERR_NO_MEMORY; > + } > + > + /* The number of resource entries in buffer is passed as 1 since only > a > + * single switch/VEB instance is freed, and hence a single VEB counter > + * is released > + */ > + counter_buf->num_elems =3D CPU_TO_LE16(1); > + counter_buf->res_type =3D > CPU_TO_LE16(ICE_AQC_RES_TYPE_VEB_COUNTER); > + counter_buf->elem[0].e.sw_resp =3D CPU_TO_LE16(counter_id); > + > + status =3D ice_aq_alloc_free_res(hw, 1, counter_buf, buf_len, > + ice_aqc_opc_free_res, NULL); > + if (status) { > + ice_debug(hw, ICE_DBG_SW, > + "VEB counter resource could not be freed\n"); > + ret_status =3D status; > + } > + > + ice_free(hw, counter_buf); > + ice_free(hw, sw_buf); > + return ret_status; > +} >=20 > /** > * ice_aq_add_vsi > diff --git a/drivers/net/ice/base/ice_switch.h > b/drivers/net/ice/base/ice_switch.h > index 66a172fc2..dd21781f7 100644 > --- a/drivers/net/ice/base/ice_switch.h > +++ b/drivers/net/ice/base/ice_switch.h > @@ -290,6 +290,11 @@ ice_free_vlan_res_counter(struct ice_hw *hw, u16 > counter_id); > /* Switch/bridge related commands */ > enum ice_status ice_update_sw_rule_bridge_mode(struct ice_hw *hw); > enum ice_status > +ice_alloc_sw(struct ice_hw *hw, bool ena_stats, bool shared_res, u16 > *sw_id, > + u16 *counter_id); > +enum ice_status > +ice_free_sw(struct ice_hw *hw, u16 sw_id, u16 counter_id); enum > +ice_status > ice_add_vlan(struct ice_hw *hw, struct LIST_HEAD_TYPE *m_list); enum > ice_status ice_add_mac(struct ice_hw *hw, struct LIST_HEAD_TYPE *m_lst); > enum ice_status ice_remove_mac(struct ice_hw *hw, struct LIST_HEAD_TYPE > *m_lst); > -- > 2.13.6