From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by dpdk.org (Postfix) with ESMTP id F0D0BB36B for ; Mon, 11 Aug 2014 10:27:35 +0200 (CEST) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga101.jf.intel.com with ESMTP; 11 Aug 2014 01:30:24 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.01,839,1400050800"; d="scan'208";a="586351434" Received: from irsmsx101.ger.corp.intel.com ([163.33.3.153]) by orsmga002.jf.intel.com with ESMTP; 11 Aug 2014 01:30:21 -0700 Received: from irsmsx107.ger.corp.intel.com (163.33.3.99) by IRSMSX101.ger.corp.intel.com (163.33.3.153) with Microsoft SMTP Server (TLS) id 14.3.195.1; Mon, 11 Aug 2014 09:30:20 +0100 Received: from irsmsx102.ger.corp.intel.com ([169.254.2.12]) by IRSMSX107.ger.corp.intel.com ([169.254.10.245]) with mapi id 14.03.0195.001; Mon, 11 Aug 2014 09:30:20 +0100 From: "Wodkowski, PawelX" To: "Zhang, Helin" Thread-Topic: SRIOV mode and different RX and TX configuration Thread-Index: Ac+1OFzBKtAM5KBZTo6WNfSE2w/DtQAA4ldgAAA/CcA= Date: Mon, 11 Aug 2014 08:30:20 +0000 Message-ID: References: In-Reply-To: Accept-Language: pl-PL, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [163.33.239.182] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Cc: "dev@dpdk.org" Subject: Re: [dpdk-dev] SRIOV mode and different RX and TX configuration X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 11 Aug 2014 08:27:36 -0000 > Do you mean the configurable number of rx/tx queues in VF? For Niantic, > hardware just supports only one queue in VF, so there is no flexibility f= or that. > For later NICs like i40e, we will have that flexibility. Yes, you are right but only in when DCB and RSS/TSS are off. When using DCB= =20 and/or RSS/TSS you have some number TCs/TSS pools x 1 queue. I am asking if configuring RX side and TX side in different mode is permitt= ed=20 and make sense. From Niantic datasheet I did not seen any restrictions on t= his. Some part of ixgbe pmd driver code make difference in that and some don't. I need to unify this in one direction before enabling DCB in SR-IOV mode. Pawel