From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by dpdk.space (Postfix) with ESMTP id 16532A0471 for ; Fri, 21 Jun 2019 16:49:34 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 65FF61D533; Fri, 21 Jun 2019 16:49:33 +0200 (CEST) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by dpdk.org (Postfix) with ESMTP id A99101D528 for ; Fri, 21 Jun 2019 16:49:31 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 21 Jun 2019 07:49:30 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.63,400,1557212400"; d="scan'208";a="312005128" Received: from fmsmsx104.amr.corp.intel.com ([10.18.124.202]) by orsmga004.jf.intel.com with ESMTP; 21 Jun 2019 07:49:30 -0700 Received: from fmsmsx126.amr.corp.intel.com (10.18.125.43) by fmsmsx104.amr.corp.intel.com (10.18.124.202) with Microsoft SMTP Server (TLS) id 14.3.439.0; Fri, 21 Jun 2019 07:49:30 -0700 Received: from fmsmsx120.amr.corp.intel.com ([169.254.15.12]) by FMSMSX126.amr.corp.intel.com ([169.254.1.119]) with mapi id 14.03.0439.000; Fri, 21 Jun 2019 07:49:30 -0700 From: "Stillwell Jr, Paul M" To: "Zhao1, Wei" , "dev@dpdk.org" CC: "Zhao1, Wei" Thread-Topic: [dpdk-dev] [PATCH v5] net/ice: enable switch filter Thread-Index: AQHVKA7AWAEfT2Dn3UeVXB4jJbSEcqamLNAg Date: Fri, 21 Jun 2019 14:49:29 +0000 Message-ID: References: <1561105343-37821-1-git-send-email-wei.zhao1@intel.com> In-Reply-To: <1561105343-37821-1-git-send-email-wei.zhao1@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ctpclassification: CTP_NT x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiNmFkN2Q1NDItZGY0OC00ODdlLWFlYmMtOTJkYzAwZWNhOTI1IiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoianV3R0w1bTEyT0QzTGdzNEtLNklhMDJ0SVhjOStzR1FsajFSeVBXU29GeENZZk1rbEl5N1wvdmlmeUZEbm1HK3cifQ== x-originating-ip: [10.1.200.106] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v5] net/ice: enable switch filter X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: dev On Behalf Of Wei Zhao > Sent: Friday, June 21, 2019 1:22 AM > To: dev@dpdk.org > Cc: Zhao1, Wei > Subject: [dpdk-dev] [PATCH v5] net/ice: enable switch filter >=20 > From: wei zhao >=20 > The patch enables the backend of rte_flow. It transfers rte_flow_xxx to > device specific data structure and configures packet process engine's bin= ary > classifier > (switch) properly. >=20 > Signed-off-by: Wei Zhao > --- > drivers/net/ice/Makefile | 1 + > drivers/net/ice/ice_ethdev.c | 18 ++ > drivers/net/ice/ice_ethdev.h | 7 + > drivers/net/ice/ice_switch_filter.c | 521 > ++++++++++++++++++++++++++++++++++++ > drivers/net/ice/ice_switch_filter.h | 24 ++ > drivers/net/ice/meson.build | 3 +- > 6 files changed, 573 insertions(+), 1 deletion(-) create mode 100644 > drivers/net/ice/ice_switch_filter.c > create mode 100644 drivers/net/ice/ice_switch_filter.h >=20 > diff --git a/drivers/net/ice/Makefile b/drivers/net/ice/Makefile index > 0e5c55e..b10d826 100644 > --- a/drivers/net/ice/Makefile > +++ b/drivers/net/ice/Makefile > @@ -60,6 +60,7 @@ ifeq ($(CONFIG_RTE_ARCH_X86), y) > SRCS-$(CONFIG_RTE_LIBRTE_ICE_PMD) +=3D ice_rxtx_vec_sse.c endif >=20 > +SRCS-$(CONFIG_RTE_LIBRTE_ICE_PMD) +=3D ice_switch_filter.c > ifeq ($(findstring > RTE_MACHINE_CPUFLAG_AVX2,$(CFLAGS)),RTE_MACHINE_CPUFLAG_AVX > 2) > CC_AVX2_SUPPORT=3D1 > else > diff --git a/drivers/net/ice/ice_ethdev.c b/drivers/net/ice/ice_ethdev.c > index d1e15ab..0382521 100644 > --- a/drivers/net/ice/ice_ethdev.c > +++ b/drivers/net/ice/ice_ethdev.c > @@ -1357,6 +1357,21 @@ static int ice_load_pkg(struct rte_eth_dev *dev) > return err; > } >=20 > +static void > +ice_base_queue_get(struct ice_pf *pf) > +{ > + uint32_t reg; > + struct ice_hw *hw =3D ICE_PF_TO_HW(pf); > + > + reg =3D ICE_READ_REG(hw, PFLAN_RX_QALLOC); > + if (reg & PFLAN_RX_QALLOC_VALID_M) { > + pf->base_queue =3D reg & PFLAN_RX_QALLOC_FIRSTQ_M; > + } else { > + PMD_INIT_LOG(WARNING, "Failed to get Rx base queue" > + " index"); > + } > +} > + > static int > ice_dev_init(struct rte_eth_dev *dev) > { > @@ -1453,6 +1468,9 @@ ice_dev_init(struct rte_eth_dev *dev) > /* enable uio intr after callback register */ > rte_intr_enable(intr_handle); >=20 > + /* get base queue pairs index in the device */ > + ice_base_queue_get(pf); > + > return 0; >=20 > err_pf_setup: > diff --git a/drivers/net/ice/ice_ethdev.h b/drivers/net/ice/ice_ethdev.h > index 1385afa..50b966c 100644 > --- a/drivers/net/ice/ice_ethdev.h > +++ b/drivers/net/ice/ice_ethdev.h > @@ -234,6 +234,12 @@ struct ice_vsi { > bool offset_loaded; > }; >=20 > +/* Struct to store flow created. */ > +struct rte_flow { > + TAILQ_ENTRY(rte_flow) node; > + void *rule; > +}; > + > struct ice_pf { > struct ice_adapter *adapter; /* The adapter this PF associate to */ > struct ice_vsi *main_vsi; /* pointer to main VSI structure */ @@ - > 252,6 +258,7 @@ struct ice_pf { > uint16_t hash_lut_size; /* The size of hash lookup table */ > uint16_t lan_nb_qp_max; > uint16_t lan_nb_qps; /* The number of queue pairs of LAN */ > + uint16_t base_queue; /* The base queue pairs index in the device > */ > struct ice_hw_port_stats stats_offset; > struct ice_hw_port_stats stats; > /* internal packet statistics, it should be excluded from the total */ > diff --git a/drivers/net/ice/ice_switch_filter.c > b/drivers/net/ice/ice_switch_filter.c > new file mode 100644 > index 0000000..41752fa > --- /dev/null > +++ b/drivers/net/ice/ice_switch_filter.c > @@ -0,0 +1,521 @@ > +/* SPDX-License-Identifier: BSD-3-Clause > + * Copyright(c) 2019 Intel Corporation > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include "ice_logs.h" > +#include "base/ice_type.h" > +#include "ice_switch_filter.h" > + > +static int > +ice_parse_switch_filter(const struct rte_flow_item pattern[], > + const struct rte_flow_action actions[], > + struct rte_flow_error *error, > + struct ice_adv_rule_info *rule_info, > + struct ice_adv_lkup_elem **lkup_list, > + uint16_t *lkups_num) > +{ > + const struct rte_flow_item *item =3D pattern; > + enum rte_flow_item_type item_type; > + const struct rte_flow_item_eth *eth_spec, *eth_mask; > + const struct rte_flow_item_ipv4 *ipv4_spec, *ipv4_mask; > + const struct rte_flow_item_ipv6 *ipv6_spec, *ipv6_mask; > + const struct rte_flow_item_tcp *tcp_spec, *tcp_mask; > + const struct rte_flow_item_udp *udp_spec, *udp_mask; > + const struct rte_flow_item_sctp *sctp_spec, *sctp_mask; > + const struct rte_flow_item_nvgre *nvgre_spec, *nvgre_mask; > + const struct rte_flow_item_vxlan *vxlan_spec, *vxlan_mask; > + struct ice_adv_lkup_elem *list; > + uint16_t j, t =3D 0; > + uint16_t item_num =3D 0; > + enum ice_sw_tunnel_type tun_type =3D ICE_NON_TUN; > + uint16_t tunnel_valid =3D 0; > + > + for (; item->type !=3D RTE_FLOW_ITEM_TYPE_END; item++) { > + if (item->type =3D=3D RTE_FLOW_ITEM_TYPE_ETH || > + item->type =3D=3D RTE_FLOW_ITEM_TYPE_IPV4 || > + item->type =3D=3D RTE_FLOW_ITEM_TYPE_IPV6 || > + item->type =3D=3D RTE_FLOW_ITEM_TYPE_UDP || > + item->type =3D=3D RTE_FLOW_ITEM_TYPE_TCP || > + item->type =3D=3D RTE_FLOW_ITEM_TYPE_SCTP || > + item->type =3D=3D RTE_FLOW_ITEM_TYPE_VXLAN || > + item->type =3D=3D RTE_FLOW_ITEM_TYPE_NVGRE) > + item_num++; > + if (item->type =3D=3D RTE_FLOW_ITEM_TYPE_VXLAN) > + tun_type =3D ICE_SW_TUN_VXLAN; > + if (item->type =3D=3D RTE_FLOW_ITEM_TYPE_NVGRE) > + tun_type =3D ICE_SW_TUN_NVGRE; should the line if (item->type =3D=3D RTE_FLOW_ITEM_TYPE_NVGRE) be else if since if it matched VXLAN it shouldn't match NVGRE? > + } > + > + list =3D rte_zmalloc(NULL, item_num * sizeof(*list), 0); > + if (!list) { > + rte_flow_error_set(error, EINVAL, > + RTE_FLOW_ERROR_TYPE_ITEM, actions, > + "No memory for PMD internal items"); > + goto out; > + } > + *lkup_list =3D list; > + > + for (item =3D pattern; item->type !=3D > + RTE_FLOW_ITEM_TYPE_END; item++) { > + item_type =3D item->type; > + > + switch (item_type) { > + case RTE_FLOW_ITEM_TYPE_ETH: > + eth_spec =3D item->spec; > + eth_mask =3D item->mask; > + if (eth_spec && eth_mask) { > + list[t].type =3D (tun_type =3D=3D ICE_NON_TUN) ? > + ICE_MAC_OFOS : ICE_MAC_IL; > + struct ice_ether_hdr *h; > + struct ice_ether_hdr *m; > + h =3D &list[t].h_u.eth_hdr; > + m =3D &list[t].m_u.eth_hdr; > + for (j =3D 0; j < RTE_ETHER_ADDR_LEN; j++) { > + if (eth_mask->src.addr_bytes[j] =3D=3D > + UINT8_MAX) > { > + h->src_addr[j] =3D > + eth_spec->src.addr_bytes[j]; > + m->src_addr[j] =3D > + eth_mask- > >src.addr_bytes[j]; > + } > + if (eth_mask->dst.addr_bytes[j] =3D=3D > + UINT8_MAX) > { > + h->dst_addr[j] =3D > + eth_spec->dst.addr_bytes[j]; > + m->dst_addr[j] =3D > + eth_mask- > >dst.addr_bytes[j]; > + } > + } > + if (eth_mask->type =3D=3D UINT16_MAX) { > + h->ethtype_id =3D > + rte_be_to_cpu_16(eth_spec->type); > + m->ethtype_id =3D UINT16_MAX; > + } > + t++; > + } else if (!eth_spec && !eth_mask) { > + list[t].type =3D (tun_type =3D=3D ICE_NON_TUN) ? > + ICE_MAC_OFOS : ICE_MAC_IL; > + } > + break; > + > + case RTE_FLOW_ITEM_TYPE_IPV4: > + ipv4_spec =3D item->spec; > + ipv4_mask =3D item->mask; > + if (ipv4_spec && ipv4_mask) { > + list[t].type =3D (tun_type =3D=3D ICE_NON_TUN) ? > + ICE_IPV4_OFOS : ICE_IPV4_IL; > + if (ipv4_mask->hdr.src_addr =3D=3D > UINT32_MAX) { > + list[t].h_u.ipv4_hdr.src_addr =3D > + ipv4_spec->hdr.src_addr; > + list[t].m_u.ipv4_hdr.src_addr =3D > + UINT32_MAX; > + } > + if (ipv4_mask->hdr.dst_addr =3D=3D > UINT32_MAX) { > + list[t].h_u.ipv4_hdr.dst_addr =3D > + ipv4_spec->hdr.dst_addr; > + list[t].m_u.ipv4_hdr.dst_addr =3D > + UINT32_MAX; > + } > + if (ipv4_mask->hdr.time_to_live =3D=3D > UINT8_MAX) { > + list[t].h_u.ipv4_hdr.time_to_live =3D > + ipv4_spec->hdr.time_to_live; > + list[t].m_u.ipv4_hdr.time_to_live =3D > + UINT8_MAX; > + } > + if (ipv4_mask->hdr.next_proto_id =3D=3D > UINT8_MAX) { > + list[t].h_u.ipv4_hdr.protocol =3D > + ipv4_spec- > >hdr.next_proto_id; > + list[t].m_u.ipv4_hdr.protocol =3D > + UINT8_MAX; > + } > + if (ipv4_mask->hdr.type_of_service =3D=3D > + UINT8_MAX) { > + list[t].h_u.ipv4_hdr.tos =3D > + ipv4_spec- > >hdr.type_of_service; > + list[t].m_u.ipv4_hdr.tos =3D > UINT8_MAX; > + } > + t++; > + } else if (!ipv4_spec && !ipv4_mask) { > + list[t].type =3D (tun_type =3D=3D ICE_NON_TUN) ? > + ICE_IPV4_OFOS : ICE_IPV4_IL; > + } > + break; > + > + case RTE_FLOW_ITEM_TYPE_IPV6: > + ipv6_spec =3D item->spec; > + ipv6_mask =3D item->mask; > + if (ipv6_spec && ipv6_mask) { > + list[t].type =3D (tun_type =3D=3D ICE_NON_TUN) ? > + ICE_IPV6_OFOS : ICE_IPV6_IL; > + struct ice_ipv6_hdr *f; > + struct ice_ipv6_hdr *s; > + f =3D &list[t].h_u.ice_ipv6_ofos_hdr; > + s =3D &list[t].m_u.ice_ipv6_ofos_hdr; > + for (j =3D 0; j < ICE_IPV6_ADDR_LENGTH; j++) { > + if (ipv6_mask->hdr.src_addr[j] =3D=3D > + UINT8_MAX) > { > + f->src_addr[j] =3D > + ipv6_spec->hdr.src_addr[j]; > + s->src_addr[j] =3D > + ipv6_mask->hdr.src_addr[j]; > + } > + if (ipv6_mask->hdr.dst_addr[j] =3D=3D > + UINT8_MAX) > { > + f->dst_addr[j] =3D > + ipv6_spec->hdr.dst_addr[j]; > + s->dst_addr[j] =3D > + ipv6_mask->hdr.dst_addr[j]; > + } > + } > + if (ipv6_mask->hdr.proto =3D=3D UINT8_MAX) { > + f->next_hdr =3D > + ipv6_spec->hdr.proto; > + s->next_hdr =3D UINT8_MAX; > + } > + if (ipv6_mask->hdr.hop_limits =3D=3D > UINT8_MAX) { > + f->hop_limit =3D > + ipv6_spec->hdr.hop_limits; > + s->hop_limit =3D UINT8_MAX; > + } > + t++; > + } else if (!ipv6_spec && !ipv6_mask) { > + list[t].type =3D (tun_type =3D=3D ICE_NON_TUN) ? > + ICE_IPV4_OFOS : ICE_IPV4_IL; > + } > + break; > + > + case RTE_FLOW_ITEM_TYPE_UDP: > + udp_spec =3D item->spec; > + udp_mask =3D item->mask; > + if (udp_spec && udp_mask) { > + if (tun_type =3D=3D ICE_SW_TUN_VXLAN && > + tunnel_valid =3D=3D 0) > + list[t].type =3D ICE_UDP_OF; > + else > + list[t].type =3D ICE_UDP_ILOS; > + if (udp_mask->hdr.src_port =3D=3D > UINT16_MAX) { > + list[t].h_u.l4_hdr.src_port =3D > + udp_spec->hdr.src_port; > + list[t].m_u.l4_hdr.src_port =3D > + udp_mask->hdr.src_port; > + } > + if (udp_mask->hdr.dst_port =3D=3D > UINT16_MAX) { > + list[t].h_u.l4_hdr.dst_port =3D > + udp_spec->hdr.dst_port; > + list[t].m_u.l4_hdr.dst_port =3D > + udp_mask->hdr.dst_port; > + } > + t++; > + } else if (!udp_spec && !udp_mask) { > + list[t].type =3D ICE_UDP_ILOS; > + } > + break; > + > + case RTE_FLOW_ITEM_TYPE_TCP: > + tcp_spec =3D item->spec; > + tcp_mask =3D item->mask; > + if (tcp_spec && tcp_mask) { > + list[t].type =3D ICE_TCP_IL; > + if (tcp_mask->hdr.src_port =3D=3D UINT16_MAX) > { > + list[t].h_u.l4_hdr.src_port =3D > + tcp_spec->hdr.src_port; > + list[t].m_u.l4_hdr.src_port =3D > + tcp_mask->hdr.src_port; > + } > + if (tcp_mask->hdr.dst_port =3D=3D UINT16_MAX) > { > + list[t].h_u.l4_hdr.dst_port =3D > + tcp_spec->hdr.dst_port; > + list[t].m_u.l4_hdr.dst_port =3D > + tcp_mask->hdr.dst_port; > + } > + t++; > + } else if (!tcp_spec && !tcp_mask) { > + list[t].type =3D ICE_TCP_IL; > + } > + break; > + > + case RTE_FLOW_ITEM_TYPE_SCTP: > + sctp_spec =3D item->spec; > + sctp_mask =3D item->mask; > + if (sctp_spec && sctp_mask) { > + list[t].type =3D ICE_SCTP_IL; > + if (sctp_mask->hdr.src_port =3D=3D > UINT16_MAX) { > + list[t].h_u.sctp_hdr.src_port =3D > + sctp_spec->hdr.src_port; > + list[t].m_u.sctp_hdr.src_port =3D > + sctp_mask->hdr.src_port; > + } > + if (sctp_mask->hdr.dst_port =3D=3D > UINT16_MAX) { > + list[t].h_u.sctp_hdr.dst_port =3D > + sctp_spec->hdr.dst_port; > + list[t].m_u.sctp_hdr.dst_port =3D > + sctp_mask->hdr.dst_port; > + } > + t++; > + } else if (!sctp_spec && !sctp_mask) { > + list[t].type =3D ICE_SCTP_IL; > + } > + break; > + > + case RTE_FLOW_ITEM_TYPE_VXLAN: > + vxlan_spec =3D item->spec; > + vxlan_mask =3D item->mask; > + tunnel_valid =3D 1; > + if (vxlan_spec && vxlan_mask) { > + list[t].type =3D ICE_VXLAN; > + if (vxlan_mask->vni[0] =3D=3D UINT8_MAX && > + vxlan_mask->vni[1] =3D=3D UINT8_MAX > && > + vxlan_mask->vni[2] =3D=3D UINT8_MAX) > { > + list[t].h_u.tnl_hdr.vni =3D > + (vxlan_spec->vni[2] << 16) | > + (vxlan_spec->vni[1] << 8) | > + vxlan_spec->vni[0]; > + list[t].m_u.tnl_hdr.vni =3D > + UINT32_MAX; > + } > + t++; > + } else if (!vxlan_spec && !vxlan_mask) { > + list[t].type =3D ICE_VXLAN; > + } > + break; > + > + case RTE_FLOW_ITEM_TYPE_NVGRE: > + nvgre_spec =3D item->spec; > + nvgre_mask =3D item->mask; > + tunnel_valid =3D 1; > + if (nvgre_spec && nvgre_mask) { > + list[t].type =3D ICE_NVGRE; > + if (nvgre_mask->tni[0] =3D=3D UINT8_MAX && > + nvgre_mask->tni[1] =3D=3D UINT8_MAX > && > + nvgre_mask->tni[2] =3D=3D UINT8_MAX) > { > + list[t].h_u.nvgre_hdr.tni_flow =3D > + (nvgre_spec->tni[2] << 16) | > + (nvgre_spec->tni[1] << 8) | > + nvgre_spec->tni[0]; > + list[t].m_u.nvgre_hdr.tni_flow =3D > + UINT32_MAX; > + } > + t++; > + } else if (!nvgre_spec && !nvgre_mask) { > + list[t].type =3D ICE_NVGRE; > + } > + break; > + > + case RTE_FLOW_ITEM_TYPE_VOID: > + case RTE_FLOW_ITEM_TYPE_END: > + break; > + > + default: > + rte_flow_error_set(error, EINVAL, > + RTE_FLOW_ERROR_TYPE_ITEM, actions, > + "Invalid pattern item."); > + goto out; > + } > + } > + > + rule_info->tun_type =3D tun_type; > + *lkups_num =3D t; > + > + return 0; > +out: > + return -rte_errno; > +} > + > +/* By now ice switch filter action code implement only Minor suggestion: By now =3D> For now > + * supports QUEUE or DROP. > + */ > +static int > +ice_parse_switch_action(struct ice_pf *pf, > + const struct rte_flow_action *actions, > + struct rte_flow_error *error, > + struct ice_adv_rule_info *rule_info) { > + struct ice_vsi *vsi =3D pf->main_vsi; > + const struct rte_flow_action_queue *act_q; > + uint16_t base_queue; > + const struct rte_flow_action *action; > + enum rte_flow_action_type action_type; > + > + base_queue =3D pf->base_queue; > + for (action =3D actions; action->type !=3D > + RTE_FLOW_ACTION_TYPE_END; action++) { > + action_type =3D action->type; > + switch (action_type) { > + case RTE_FLOW_ACTION_TYPE_QUEUE: > + act_q =3D action->conf; > + rule_info->sw_act.fltr_act =3D > + ICE_FWD_TO_Q; > + rule_info->sw_act.fwd_id.q_id =3D > + base_queue + act_q->index; > + if (act_q->index >=3D > + pf->dev_data->nb_rx_queues) { > + rte_flow_error_set(error, > + EINVAL, > + RTE_FLOW_ERROR_TYPE_ACTION, > + actions, "Invalid queue ID" > + " for switch filter."); > + return -rte_errno; > + } > + break; > + > + case RTE_FLOW_ACTION_TYPE_DROP: > + rule_info->sw_act.fltr_act =3D > + ICE_DROP_PACKET; > + break; > + > + case RTE_FLOW_ACTION_TYPE_VOID: > + break; > + > + default: > + rte_flow_error_set(error, > + EINVAL, > + RTE_FLOW_ERROR_TYPE_ITEM, > + actions, > + "Invalid action type"); > + return -rte_errno; > + } > + } > + > + rule_info->sw_act.vsi_handle =3D vsi->idx; > + rule_info->rx =3D 1; > + rule_info->sw_act.src =3D vsi->idx; > + > + return 0; > +} > + > +static int > +ice_switch_rule_set(struct ice_pf *pf, > + struct ice_adv_lkup_elem *list, > + uint16_t lkups_cnt, > + struct ice_adv_rule_info *rule_info, > + struct rte_flow *flow, > + struct rte_flow_error *error) > +{ > + struct ice_hw *hw =3D ICE_PF_TO_HW(pf); > + int ret; > + struct ice_rule_query_data rule_added =3D {0}; > + struct ice_rule_query_data *filter_ptr; > + > + if (lkups_cnt > ICE_MAX_CHAIN_WORDS) { > + rte_flow_error_set(error, EINVAL, > + RTE_FLOW_ERROR_TYPE_ITEM, NULL, > + "item number too large for rule"); > + return -rte_errno; > + } > + if (!list) { > + rte_flow_error_set(error, EINVAL, > + RTE_FLOW_ERROR_TYPE_ITEM, NULL, > + "lookup list should not be NULL"); > + return -rte_errno; > + } > + > + ret =3D ice_add_adv_rule(hw, list, lkups_cnt, rule_info, &rule_added); > + > + if (!ret) { > + filter_ptr =3D rte_zmalloc("ice_switch_filter", > + sizeof(struct ice_rule_query_data), 0); > + if (!filter_ptr) { > + PMD_DRV_LOG(ERR, "failed to allocate memory"); > + return -EINVAL; > + } > + flow->rule =3D filter_ptr; > + rte_memcpy(filter_ptr, > + &rule_added, > + sizeof(struct ice_rule_query_data)); > + } > + > + return ret; > +} > + > +int > +ice_create_switch_filter(struct ice_pf *pf, > + const struct rte_flow_item pattern[], > + const struct rte_flow_action actions[], > + struct rte_flow *flow, > + struct rte_flow_error *error) > +{ > + int ret =3D 0; > + struct ice_adv_rule_info rule_info =3D {0}; > + struct ice_adv_lkup_elem *list =3D NULL; > + uint16_t lkups_num =3D 0; > + > + ret =3D ice_parse_switch_filter(pattern, actions, error, > + &rule_info, &list, &lkups_num); > + if (ret) > + goto error; > + > + ret =3D ice_parse_switch_action(pf, actions, error, &rule_info); > + if (ret) > + goto error; > + > + ret =3D ice_switch_rule_set(pf, list, lkups_num, &rule_info, flow, > error); > + if (ret) > + goto error; > + > + rte_free(list); > + return 0; > + > +error: > + rte_free(list); > + > + return -rte_errno; > +} > + > +int > +ice_destroy_switch_filter(struct ice_pf *pf, > + struct rte_flow *flow, > + struct rte_flow_error *error) > +{ > + struct ice_hw *hw =3D ICE_PF_TO_HW(pf); > + int ret; > + struct ice_rule_query_data *filter_ptr; > + > + filter_ptr =3D (struct ice_rule_query_data *) > + flow->rule; > + > + if (!filter_ptr) { > + rte_flow_error_set(error, EINVAL, > + RTE_FLOW_ERROR_TYPE_HANDLE, NULL, > + "no such flow" > + " create by switch filter"); > + return -rte_errno; > + } > + > + ret =3D ice_rem_adv_rule_by_id(hw, filter_ptr); > + if (ret) { > + rte_flow_error_set(error, EINVAL, > + RTE_FLOW_ERROR_TYPE_HANDLE, NULL, > + "fail to destroy switch filter rule"); > + return -rte_errno; > + } > + > + rte_free(filter_ptr); > + return ret; > +} > + > +void > +ice_free_switch_filter_rule(void *rule) { > + struct ice_rule_query_data *filter_ptr; > + > + filter_ptr =3D (struct ice_rule_query_data *)rule; > + > + rte_free(filter_ptr); > +} > diff --git a/drivers/net/ice/ice_switch_filter.h > b/drivers/net/ice/ice_switch_filter.h > new file mode 100644 > index 0000000..cea4799 > --- /dev/null > +++ b/drivers/net/ice/ice_switch_filter.h > @@ -0,0 +1,24 @@ > +/* SPDX-License-Identifier: BSD-3-Clause > + * Copyright(c) 2019 Intel Corporation > + */ > + > +#ifndef _ICE_SWITCH_FILTER_H_ > +#define _ICE_SWITCH_FILTER_H_ > + > +#include "base/ice_switch.h" > +#include "base/ice_type.h" > +#include "ice_ethdev.h" > + > +int > +ice_create_switch_filter(struct ice_pf *pf, > + const struct rte_flow_item pattern[], > + const struct rte_flow_action actions[], > + struct rte_flow *flow, > + struct rte_flow_error *error); > +int > +ice_destroy_switch_filter(struct ice_pf *pf, > + struct rte_flow *flow, > + struct rte_flow_error *error); > +void > +ice_free_switch_filter_rule(void *rule); #endif /* > +_ICE_SWITCH_FILTER_H_ */ > diff --git a/drivers/net/ice/meson.build b/drivers/net/ice/meson.build in= dex > 2bec688..8697676 100644 > --- a/drivers/net/ice/meson.build > +++ b/drivers/net/ice/meson.build > @@ -6,7 +6,8 @@ objs =3D [base_objs] >=20 > sources =3D files( > 'ice_ethdev.c', > - 'ice_rxtx.c' > + 'ice_rxtx.c', > + 'ice_switch_filter.c' > ) >=20 > deps +=3D ['hash'] > -- > 2.7.5