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Wed, 4 Apr 2018 11:11:27 +0000 From: Shreyansh Jain To: "Richardson, Bruce" , "Xu, Rosen" , "dev@dpdk.org" CC: "Doherty, Declan" , "Yigit, Ferruh" , "Ananyev, Konstantin" , "Zhang, Tianfei" , "Wu, Hao" , "gaetan.rivet@6wind.com" Thread-Topic: [PATCH v5 0/3] Introduce Intel FPGA BUS Thread-Index: AQHTy+EI0CMXOCyzI0yrFj/LKNGRFaPwYeJggAAIfgCAAAiLQA== Date: Wed, 4 Apr 2018 11:11:21 +0000 Deferred-Delivery: Wed, 4 Apr 2018 11:11:07 +0000 Message-ID: References: <1521553556-62982-1-git-send-email-rosen.xu@intel.com> <1522824677-86958-1-git-send-email-rosen.xu@intel.com> <59AF69C657FD0841A61C55336867B5B07227141A@IRSMSX103.ger.corp.intel.com> In-Reply-To: <59AF69C657FD0841A61C55336867B5B07227141A@IRSMSX103.ger.corp.intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [92.121.36.197] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; HE1PR0402MB3419; 7:LAVcFoNnGdRh98rmyjwsKeXuakISwdN+pWkoDIIQ7kTMZHQz3WLE/5kqzS3JQ5hruVHPpt3ngYEFLxablC4j3vZ4bYi3Tk6dGgzWb2hemPScO9Y7jfq3Z9YxwEwpiRN2StJD9UA7zI9zS1J+j3077tHpEPUt1WrFhhGUPCS6525U5OFr+fFvReT5t48vooQmG3IfUH3VL9hmKfNpA0hTIMHRaVChF0HXBPwepkR+dUqyxNacZYXRVkpNTyrETOtU x-ms-exchange-antispam-srfa-diagnostics: SOS; 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DIR:OUT; SFP:1101; SCL:1; SRVR:HE1PR0402MB3419; H:HE1PR0402MB2780.eurprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) authentication-results: spf=none (sender IP is ) smtp.mailfrom=shreyansh.jain@nxp.com; x-microsoft-antispam-message-info: C4IqUd8xynF5wp8ZQ6BlEF1lxJRcqek9RLPrtAMF4OSpEs8cFUSfmSJQ4FGGzOsqj6+x+mDSFQYqFmGt4QSm3a3QwKvfa1w+tCCkaLmqgA3uKMk7RWnGtRHAW4lIftU8sMV5fols//J1iJ4FQuAYf2XtzXocQ1kW59QrxFiQCDOLP2gmoExlVN9kIu/rpftTyQTl6agnTeMFEDHGx1Eh9j7auIG+3c5GbOt0qXvYSf5Eu8zy1UdAGxeU7IhNDZm/Ew/XXBxD0lKD7RJycBzFGgxZXwDMc4YUkCeHaQdSHp4/bB/rhMexkmZh9tKdYtDjI9Izy/3jSAUWYZPgC7DYd3nSuS9SyglIwdhR3PWCJgrl0yNfCIj8YisKHhJb9njeHg8WkWz0icIkaO4Yf8O0fvcTWnxuthKr4RKBONWIV2k= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 4e0b1935-9b30-407f-f68a-08d59a1ccf8a X-MS-Exchange-CrossTenant-originalarrivaltime: 04 Apr 2018 11:11:27.2983 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: HE1PR0402MB3419 Subject: Re: [dpdk-dev] [PATCH v5 0/3] Introduce Intel FPGA BUS X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 04 Apr 2018 11:11:29 -0000 > -----Original Message----- > From: Richardson, Bruce [mailto:bruce.richardson@intel.com] > Sent: Wednesday, April 4, 2018 4:08 PM > To: Shreyansh Jain ; Xu, Rosen > ; dev@dpdk.org > Cc: Doherty, Declan ; Yigit, Ferruh > ; Ananyev, Konstantin > ; Zhang, Tianfei > ; Wu, Hao ; > gaetan.rivet@6wind.com > Subject: RE: [PATCH v5 0/3] Introduce Intel FPGA BUS >=20 >=20 >=20 > > -----Original Message----- > > From: Shreyansh Jain [mailto:shreyansh.jain@nxp.com] > > Sent: Wednesday, April 4, 2018 11:14 AM > > To: Xu, Rosen ; dev@dpdk.org > > Cc: Doherty, Declan ; Richardson, Bruce > > ; Yigit, Ferruh ; > > Ananyev, Konstantin ; Zhang, Tianfei > > ; Wu, Hao ; > > gaetan.rivet@6wind.com > > Subject: RE: [PATCH v5 0/3] Introduce Intel FPGA BUS > > > > Hello Rosen, > > > > > -----Original Message----- > > > From: Rosen Xu [mailto:rosen.xu@intel.com] > > > Sent: Wednesday, April 4, 2018 12:21 PM > > > To: dev@dpdk.org > > > Cc: declan.doherty@intel.com; bruce.richardson@intel.com; Shreyansh > > > Jain ; ferruh.yigit@intel.com; > > > konstantin.ananyev@intel.com; tianfei.zhang@intel.com; > > > hao.wu@intel.com; gaetan.rivet@6wind.com > > > Subject: [PATCH v5 0/3] Introduce Intel FPGA BUS > > > > > > Intel FPGA BUS in DPDK > > > ------------------------- > > > > > > This patch set introduces Intel FPGA BUS support in DPDK. > > > > > > v5 updates: > > > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > > > - Fixed SHARED LIB Build issue > > > - Changed command name to IFPGA Rawdev name, > > > so remove pci library datastruct and function. > > > - Fixed PATCH v2/v3/v4 comments > > > > > > > [...] > > > > Primary problems I see with your patches: > > 1. They are not split enough. Still the patch 2/3 is dependent on 3/3. > > That mean, it would break the compilation. There is no simpler way to > > solve this except breaking the patch into multiple patches and slowly > > introducing each function/feature. > > (One obvious way would be to have 3/3 as 2/3 and vice-versa - Not > sure > > what that blocks). > > > > 2. Documentation - there is none right now. Being a special use case > for > > PCI, I think a lot of people would benefit if you can explain the > comments > > about why iFPGA bus is required through documentation. > > > > 3. Meson as requested by Bruce. Problem you will face is that rawdev > > doesn't yet have meson enabled. I will work on that. If you can still > > rework your patches for (1)+(2), I think meson enable over rawdev > would be > > trivial. >=20 > I just spotted this and I've sent a patch for rawdev. It was pretty > trivial. :-) > Please review and ack if you have the chance. The skeleton rawdev > however, I haven't > done, so feel free to patch in that. :) Thanks. I'll review. I will push a dependent patch for skeleton_rawdev. >=20 > /Bruce