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Wed, 6 Dec 2017 17:24:22 +0000 From: Matan Azrad To: Adrien Mazarguil CC: "dev@dpdk.org" Thread-Topic: [PATCH v2 7/8] net/mlx4: align Tx descriptors number Thread-Index: AQHTbq58y0nJ0Q074kW1wXjkU2uJ6qM2kDNw Date: Wed, 6 Dec 2017 17:24:22 +0000 Message-ID: References: <1511871570-16826-1-git-send-email-matan@mellanox.com> <1512571693-15338-1-git-send-email-matan@mellanox.com> <1512571693-15338-8-git-send-email-matan@mellanox.com> <20171206162247.GI4062@6wind.com> In-Reply-To: <20171206162247.GI4062@6wind.com> Accept-Language: en-US, he-IL Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=matan@mellanox.com; x-originating-ip: [193.47.165.251] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; HE1PR0502MB3659; 6:0hv/JkcNjS7OOYFWqhAY39YjZQ4z5UMGOS9j7PFE02T90+ZVV9QMhwDafLETULeVFdHVJHllkytwHzHqSp0rXpilfrMBUDurY89yRNChDLJetKt3V9I/LhQUybpYPaEcISRE4kAvs0TG3DVDiFhP1bnITmZUvuY7No+0sJG4KxDCYBcxzijPusLS4ZdsE3uAfL40Zl+VEiGuiDQKTrJER+Kt0MjzKmpxAm06xqS1fTywmfnf5dMIHtPN9vx7Oss4kYE+cgcYSi+MAJL1QSM/LgKNDIAN2IsdDtEXFDKjvNrYg6brhj2RvXZIFuQ/E7S+saDZWZU9Nn/c1Uo0ingIGjifPWgPl9Hf/nltRZhdAwY=; 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DIR:OUT; SFP:1101; SCL:1; SRVR:HE1PR0502MB3659; H:HE1PR0502MB3659.eurprd05.prod.outlook.com; FPR:; SPF:None; PTR:InfoNoRecords; MX:1; A:1; LANG:en; received-spf: None (protection.outlook.com: mellanox.com does not designate permitted sender hosts) spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: Mellanox.com X-MS-Exchange-CrossTenant-Network-Message-Id: 2080366d-f0da-4176-7082-08d53cce3137 X-MS-Exchange-CrossTenant-originalarrivaltime: 06 Dec 2017 17:24:22.7720 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: a652971c-7d2e-4d9b-a6a4-d149256f461b X-MS-Exchange-Transport-CrossTenantHeadersStamped: HE1PR0502MB3659 Subject: Re: [dpdk-dev] [PATCH v2 7/8] net/mlx4: align Tx descriptors number X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 06 Dec 2017 17:24:24 -0000 Hi Adrien > -----Original Message----- > From: Adrien Mazarguil [mailto:adrien.mazarguil@6wind.com] > Sent: Wednesday, December 6, 2017 6:23 PM > To: Matan Azrad > Cc: dev@dpdk.org > Subject: Re: [PATCH v2 7/8] net/mlx4: align Tx descriptors number >=20 > On Wed, Dec 06, 2017 at 02:48:12PM +0000, Matan Azrad wrote: > > Using power of 2 descriptors number makes the ring management easier > > and allows to use mask operation instead of wraparound conditions. > > > > Adjust Tx descriptor number to be power of 2 and change calculation to > > use mask accordingly. > > > > Signed-off-by: Matan Azrad > > --- > > drivers/net/mlx4/mlx4_rxtx.c | 28 +++++++++++++--------------- > > drivers/net/mlx4/mlx4_txq.c | 13 +++++++++---- > > 2 files changed, 22 insertions(+), 19 deletions(-) > > > > diff --git a/drivers/net/mlx4/mlx4_rxtx.c > > b/drivers/net/mlx4/mlx4_rxtx.c index 8b8d95e..14192fe 100644 > > --- a/drivers/net/mlx4/mlx4_rxtx.c > > +++ b/drivers/net/mlx4/mlx4_rxtx.c > > @@ -312,10 +312,14 @@ struct pv { > > * > > * @param txq > > * Pointer to Tx queue structure. > > + * @param sq > > + * Pointer to the SQ structure. > > + * @param elts_m > > + * Tx elements number mask. >=20 > It's minor however these parameters should be described in the same order > as they appear in the function prototype, please swap them if you send an > updated series. >=20 > > */ > > static void > > -mlx4_txq_complete(struct txq *txq, const unsigned int elts_n, > > - struct mlx4_sq *sq) > > +mlx4_txq_complete(struct txq *txq, const unsigned int elts_m, > > + struct mlx4_sq *sq) > > { > > > diff --git a/drivers/net/mlx4/mlx4_txq.c b/drivers/net/mlx4/mlx4_txq.c > > index 4c7b62a..7eb4b04 100644 > > --- a/drivers/net/mlx4/mlx4_txq.c > > +++ b/drivers/net/mlx4/mlx4_txq.c > > @@ -76,17 +76,16 @@ > > unsigned int elts_head =3D txq->elts_head; > > unsigned int elts_tail =3D txq->elts_tail; > > struct txq_elt (*elts)[txq->elts_n] =3D txq->elts; > > + unsigned int elts_m =3D txq->elts_n - 1; > > > > DEBUG("%p: freeing WRs", (void *)txq); > > while (elts_tail !=3D elts_head) { > > - struct txq_elt *elt =3D &(*elts)[elts_tail]; > > + struct txq_elt *elt =3D &(*elts)[elts_tail++ & elts_m]; > > > > assert(elt->buf !=3D NULL); > > rte_pktmbuf_free(elt->buf); > > elt->buf =3D NULL; > > elt->wqe =3D NULL; > > - if (++elts_tail =3D=3D RTE_DIM(*elts)) > > - elts_tail =3D 0; > > } > > txq->elts_tail =3D txq->elts_head; > > } > > @@ -208,7 +207,7 @@ struct txq_mp2mr_mbuf_check_data { > > struct mlx4dv_obj mlxdv; > > struct mlx4dv_qp dv_qp; > > struct mlx4dv_cq dv_cq; > > - struct txq_elt (*elts)[desc]; > > + struct txq_elt (*elts)[rte_align32pow2(desc)]; >=20 > OK, I'm curious about what happened to the magic 0x1000 though? Was it a > limitation or some leftover debugging code? >=20 Wrong limitation to the max number of descriptors. Thanks again for the second good review. Will adjust all your comments for = v3. > -- > Adrien Mazarguil > 6WIND