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CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; CAT:NONE; SFS:(4636009)(376002)(346002)(396003)(136003)(39850400004)(36840700001)(46966006)(26005)(82740400003)(8936002)(356005)(82310400003)(81166007)(33656002)(36860700001)(186003)(8676002)(316002)(110136005)(52536014)(54906003)(450100002)(4326008)(6506007)(55016002)(53546011)(47076005)(2906002)(83380400001)(7696005)(5660300002)(478600001)(70586007)(336012)(70206006)(86362001)(9686003); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Jul 2021 06:00:18.7519 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 00f208e9-7f6c-4de4-aed2-08d9429ed488 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DB5EUR03FT004.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR08MB4173 Subject: Re: [dpdk-dev] [PATCH] net/bnxt: fix missing barriers in completion handling X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: Lance Richardson > Sent: Friday, July 9, 2021 3:15 AM > To: Ajit Khaparde (ajit.khaparde@broadcom.com) > ; Somnath Kotur > ; Bruce Richardson > ; Konstantin Ananyev > ; jerinj@marvell.com; Ruifeng Wang > ; Stephen Hurd ; > David Christensen > Cc: dev@dpdk.org; stable@dpdk.org > Subject: [PATCH] net/bnxt: fix missing barriers in completion handling >=20 > Ensure that Rx/Tx/Async completion entry fields are accessed > only after the completion's valid flag has been loaded and > verified. This is needed for correct operation on systems that > use relaxed memory consistency models. >=20 > Fixes: 2eb53b134aae ("net/bnxt: add initial Rx code") > Fixes: 6eb3cc2294fd ("net/bnxt: add initial Tx code") > Cc: stable@dpdk.org > Signed-off-by: Lance Richardson > Reviewed-by: Ajit Khaparde > --- > drivers/net/bnxt/bnxt_cpr.h | 36 ++++++++++++++++++++++++--- > drivers/net/bnxt/bnxt_ethdev.c | 16 ++++++------ > drivers/net/bnxt/bnxt_irq.c | 7 +++--- > drivers/net/bnxt/bnxt_rxr.c | 9 ++++--- > drivers/net/bnxt/bnxt_rxtx_vec_avx2.c | 2 +- > drivers/net/bnxt/bnxt_rxtx_vec_neon.c | 2 +- > drivers/net/bnxt/bnxt_rxtx_vec_sse.c | 2 +- > drivers/net/bnxt/bnxt_txr.c | 2 +- > 8 files changed, 54 insertions(+), 22 deletions(-) >=20 > diff --git a/drivers/net/bnxt/bnxt_cpr.h b/drivers/net/bnxt/bnxt_cpr.h > index 2a56ec52c..3ee6b74bc 100644 > --- a/drivers/net/bnxt/bnxt_cpr.h > +++ b/drivers/net/bnxt/bnxt_cpr.h > @@ -8,13 +8,10 @@ > #include >=20 > #include > +#include "hsi_struct_def_dpdk.h" >=20 > struct bnxt_db_info; >=20 > -#define CMP_VALID(cmp, raw_cons, ring) > \ > - (!!(rte_le_to_cpu_32(((struct cmpl_base *)(cmp))->info3_v) & > \ > - CMPL_BASE_V) =3D=3D !((raw_cons) & ((ring)->ring_size))) > - > #define CMP_TYPE(cmp) \ > (((struct cmpl_base *)cmp)->type & CMPL_BASE_TYPE_MASK) >=20 > @@ -121,4 +118,35 @@ bool bnxt_is_recovery_enabled(struct bnxt *bp); > bool bnxt_is_master_func(struct bnxt *bp); >=20 > void bnxt_stop_rxtx(struct bnxt *bp); > + > +/** > + * Check validity of a completion ring entry. If the entry is valid, inc= lude a > + * C11 __ATOMIC_ACQUIRE fence to ensure that subsequent loads of fields > in the > + * completion are not hoisted by the compiler or by the CPU to come befo= re > the > + * loading of the "valid" field. > + * > + * Note: the caller must not access any fields in the specified completi= on > + * entry prior to calling this function. > + * > + * @param cmp Nit, cmpl > + * Pointer to an entry in the completion ring. > + * @param raw_cons > + * Raw consumer index of entry in completion ring. > + * @param ring_size > + * Size of completion ring. > + */ > +static __rte_always_inline bool > +bnxt_cpr_cmp_valid(const void *cmpl, uint32_t raw_cons, uint32_t > ring_size) > +{ > + const struct cmpl_base *c =3D cmpl; > + bool expected, valid; > + > + expected =3D !(raw_cons & ring_size); > + valid =3D !!(rte_le_to_cpu_32(c->info3_v) & CMPL_BASE_V); > + if (valid =3D=3D expected) { > + rte_atomic_thread_fence(__ATOMIC_ACQUIRE); > + return true; > + } > + return false; > +} > #endif > diff --git a/drivers/net/bnxt/bnxt_ethdev.c > b/drivers/net/bnxt/bnxt_ethdev.c > index ed09f1bf5..ee6929692 100644 > --- a/drivers/net/bnxt/bnxt_ethdev.c > +++ b/drivers/net/bnxt/bnxt_ethdev.c >=20 > /* Check to see if hw has posted a completion for the descriptor. */ > @@ -3327,7 +3327,7 @@ bnxt_tx_descriptor_status_op(void *tx_queue, > uint16_t offset) > cons =3D RING_CMPL(ring_mask, raw_cons); > txcmp =3D (struct tx_cmpl *)&cp_desc_ring[cons]; >=20 > - if (!CMP_VALID(txcmp, raw_cons, cp_ring_struct)) > + if (!bnxt_cpr_cmp_valid(txcmp, raw_cons, ring_mask + 1)) cpr->cp_ring_struct->ring_size can be used instead of 'ring_mask + 1'? > break; >=20 > if (CMP_TYPE(txcmp) =3D=3D TX_CMPL_TYPE_TX_L2) > diff --git a/drivers/net/bnxt/bnxt_rxtx_vec_neon.c > b/drivers/net/bnxt/bnxt_rxtx_vec_neon.c > index 263e6ec3c..13211060c 100644 > --- a/drivers/net/bnxt/bnxt_rxtx_vec_neon.c > +++ b/drivers/net/bnxt/bnxt_rxtx_vec_neon.c > @@ -339,7 +339,7 @@ bnxt_handle_tx_cp_vec(struct bnxt_tx_queue *txq) > cons =3D RING_CMPL(ring_mask, raw_cons); > txcmp =3D (struct tx_cmpl *)&cp_desc_ring[cons]; >=20 > - if (!CMP_VALID(txcmp, raw_cons, cp_ring_struct)) > + if (!bnxt_cpr_cmp_valid(txcmp, raw_cons, ring_mask + 1)) Same here. I think cpr->cp_ring_struct->ring_size can be used and it avoids= calculation. Also some places in other vector files. > break; >=20 > if (likely(CMP_TYPE(txcmp) =3D=3D TX_CMPL_TYPE_TX_L2)) > diff --git a/drivers/net/bnxt/bnxt_rxtx_vec_sse.c > b/drivers/net/bnxt/bnxt_rxtx_vec_sse.c > index 9a53d1fba..6e5630532 100644 > --- a/drivers/net/bnxt/bnxt_rxtx_vec_sse.c > +++ b/drivers/net/bnxt/bnxt_rxtx_vec_sse.c > @@ -320,7 +320,7 @@ bnxt_handle_tx_cp_vec(struct bnxt_tx_queue *txq) > cons =3D RING_CMPL(ring_mask, raw_cons); > txcmp =3D (struct tx_cmpl *)&cp_desc_ring[cons]; >=20 > - if (!CMP_VALID(txcmp, raw_cons, cp_ring_struct)) > + if (!bnxt_cpr_cmp_valid(txcmp, raw_cons, ring_mask + 1)) > break; >=20 > if (likely(CMP_TYPE(txcmp) =3D=3D TX_CMPL_TYPE_TX_L2)) > diff --git a/drivers/net/bnxt/bnxt_txr.c b/drivers/net/bnxt/bnxt_txr.c > index 9a6b96e04..47824334a 100644 > --- a/drivers/net/bnxt/bnxt_txr.c > +++ b/drivers/net/bnxt/bnxt_txr.c > @@ -461,7 +461,7 @@ static int bnxt_handle_tx_cp(struct bnxt_tx_queue > *txq) > cons =3D RING_CMPL(ring_mask, raw_cons); > txcmp =3D (struct tx_cmpl *)&cpr->cp_desc_ring[cons]; >=20 > - if (!CMP_VALID(txcmp, raw_cons, cp_ring_struct)) > + if (!bnxt_cpr_cmp_valid(txcmp, raw_cons, ring_mask + 1)) > break; >=20 > opaque =3D rte_le_to_cpu_32(txcmp->opaque); > -- > 2.25.1