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From: Slava Ovsiienko <viacheslavo@nvidia.com>
To: Igor Gutorov <igootorov@gmail.com>
Cc: "dev@dpdk.org" <dev@dpdk.org>,
	Dariusz Sosnowski <dsosnowski@nvidia.com>,
	 Matan Azrad <matan@nvidia.com>, Ori Kam <orika@nvidia.com>,
	Suanming Mou <suanmingm@nvidia.com>
Subject: RE: [PATCH v2 0/1] net/mlx5: fix incorrect rx/tx descriptor limitations in rte_eth_dev_info
Date: Sun, 23 Jun 2024 11:34:17 +0000	[thread overview]
Message-ID: <IA1PR12MB807824F2008B2D750A4CCCC4DFCB2@IA1PR12MB8078.namprd12.prod.outlook.com> (raw)
In-Reply-To: <20240618225642.1036624-1-igootorov@gmail.com>

Hi, Igor

Thank you for the v2. The patch looks good to me,  please see my further comments below.

> > 1. The absolute max descriptor number supported by ConnectX hardware is
> 32768.
> > 2. The actual max descriptor number supported by the port (and its related
> representors)
> >     reported in log_max_wq_sz in HCA.caps.  This value should be queried and
> save in mlx5_devx_cmd_query_hca_attr() routine.
> > 3. mlx5_rx_queue_pre_setup() should check requested descriptor number
> > and reject if it exceeds log_max_wq_sz
> 
> Thank you for the guidelines! I've also added the same check to
> mlx5_tx_queue_pre_setup(), I'm assuming log_max_wq_sz can be used for
> both RX and TX.
> 
> Is an `int` appropriate for `log_max_wq_sz`? Seems like a `uint8_t` is sufficient,
> but I've left it an `int` for consistency with the other `log_max_*` values.

Right, uint8_t looks to be enough. No objection to optimize others to uint8_t.

> Also, I've noticed a similar issue with MTU, it is also reported as 65535 in
> `rte_eth_dev_info.max_mtu`. I'd like to send a separate patch to fix that too.
> What's the procedure for reading max supported MTU?

MTU is not reported directly by HCA. It is per port settings and can be read from
PMTU - Port MTU Register.  ACCESS_REGISTER command should be used.
Please, see:
 https://network.nvidia.com/files/doc-2020/ethernet-adapters-programming-manual.pdf

And thorough  testing of accessing this register is needed - over physical port,
over the representors, over the VFs and SFs. Rollback to 0xFFFF should be implemented,
if register can't be accessed.

Also, this reported max MTU might be not supported for SFs/VFs, where MTU is defined
by hypervisor settings.

> 
> > 4. Please, format your patch according to the "fix" template.
> 
> I've reworded the commit message a little bit. But I don't see these issues on
> Bugzilla, I've stumbled upon them independently. If you'd like the bug reports to
> be created, let me know.

I meant this: https://doc.dpdk.org/guides/contributing/patches.html
Please see chapter "8.7. Commit Messages: Body" about "Fixes" and "Cc: stable@dpdk.org".

Also, please run checking script: /devtools/check-git-log.sh' -1 to verify commit message compliance.

With best regards,
Slava


      parent reply	other threads:[~2024-06-23 11:34 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-06-16 17:38 [PATCH 0/1] net/mlx5: show rx/tx descriptor ring " Igor Gutorov
2024-06-16 17:38 ` [PATCH 1/1] " Igor Gutorov
2024-06-17  7:18   ` Slava Ovsiienko
2024-06-18 22:56     ` [PATCH v2 0/1] net/mlx5: fix incorrect rx/tx descriptor " Igor Gutorov
2024-06-18 22:56       ` [PATCH v2] " Igor Gutorov
2024-06-23 11:34       ` Slava Ovsiienko [this message]

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