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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: IA1PR12MB8078.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 31a4c6a4-59ef-470a-952a-08dc8e9dc1ac X-MS-Exchange-CrossTenant-originalarrivaltime: 17 Jun 2024 07:18:58.9963 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: OmOkNMD3bXUYKk81IymU92D1Mb8jUN+oWjLI6cyEmQjHDbuBrfxvL33gk/u5A8YBhQO1lAHnxoz+W1BScHutag== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB9192 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Hi, Igor Thank you for the patch. 1. The absolute max descriptor number supported by ConnectX hardware is 327= 68. 2. The actual max descriptor number supported by the port (and its related = representors) reported in log_max_wq_sz in HCA.caps. This value should be queried an= d save in mlx5_devx_cmd_query_hca_attr() routine. 3. mlx5_rx_queue_pre_setup() should check requested descriptor number and r= eject if it exceeds log_max_wq_sz 4. Please, format your patch according to the "fix" template. With best regards, Slava > -----Original Message----- > From: Igor Gutorov > Sent: Sunday, June 16, 2024 8:38 PM > To: Dariusz Sosnowski ; Slava Ovsiienko > ; Ori Kam ; Suanming Mou > ; Matan Azrad > Cc: dev@dpdk.org; Igor Gutorov > Subject: [PATCH 1/1] net/mlx5: show rx/tx descriptor ring limitations in > rte_eth_dev_info >=20 > Currently, rte_eth_dev_info.rx_desc_lim.nb_max shows 65535 as a limit, wh= ich > results in a few problems: >=20 > * It is an incorrect value > * Allocating an RX queue and passing `rx_desc_lim.nb_max` results in an > integer overflow and 0 ring size: >=20 > ``` > rte_eth_rx_queue_setup(0, 0, rx_desc_lim.nb_max, 0, NULL, mb_pool); ``` >=20 > Which overflows ring size and generates the following log: > ``` > mlx5_net: port 0 increased number of descriptors in Rx queue 0 to the nex= t > power of two (0) ``` >=20 > This patch fixes these issues. >=20 > Signed-off-by: Igor Gutorov > --- > drivers/net/mlx5/mlx5_defs.h | 3 +++ > drivers/net/mlx5/mlx5_ethdev.c | 5 ++++- > 2 files changed, 7 insertions(+), 1 deletion(-) >=20 > diff --git a/drivers/net/mlx5/mlx5_defs.h b/drivers/net/mlx5/mlx5_defs.h = index > dc5216cb24..df608f0921 100644 > --- a/drivers/net/mlx5/mlx5_defs.h > +++ b/drivers/net/mlx5/mlx5_defs.h > @@ -84,6 +84,9 @@ > #define MLX5_RX_DEFAULT_BURST 64U > #define MLX5_TX_DEFAULT_BURST 64U >=20 > +/* Maximum number of descriptors in an RX/TX ring */ #define > +MLX5_MAX_RING_DESC 8192 > + > /* Number of packets vectorized Rx can simultaneously process in a loop.= */ > #define MLX5_VPMD_DESCS_PER_LOOP 4 >=20 > diff --git a/drivers/net/mlx5/mlx5_ethdev.c b/drivers/net/mlx5/mlx5_ethde= v.c > index aea799341c..d5be1ff1aa 100644 > --- a/drivers/net/mlx5/mlx5_ethdev.c > +++ b/drivers/net/mlx5/mlx5_ethdev.c > @@ -22,6 +22,7 @@ >=20 > #include >=20 > +#include "mlx5_defs.h" > #include "mlx5_rxtx.h" > #include "mlx5_rx.h" > #include "mlx5_tx.h" > @@ -345,6 +346,8 @@ mlx5_dev_infos_get(struct rte_eth_dev *dev, struct > rte_eth_dev_info *info) > info->flow_type_rss_offloads =3D ~MLX5_RSS_HF_MASK; > mlx5_set_default_params(dev, info); > mlx5_set_txlimit_params(dev, info); > + info->rx_desc_lim.nb_max =3D MLX5_MAX_RING_DESC; > + info->tx_desc_lim.nb_max =3D MLX5_MAX_RING_DESC; > if (priv->sh->cdev->config.hca_attr.mem_rq_rmp && > priv->obj_ops.rxq_obj_new =3D=3D devx_obj_ops.rxq_obj_new) > info->dev_capa |=3D RTE_ETH_DEV_CAPA_RXQ_SHARE; @@ - > 774,7 +777,7 @@ mlx5_hairpin_cap_get(struct rte_eth_dev *dev, struct > rte_eth_hairpin_cap *cap) > cap->max_nb_queues =3D UINT16_MAX; > cap->max_rx_2_tx =3D 1; > cap->max_tx_2_rx =3D 1; > - cap->max_nb_desc =3D 8192; > + cap->max_nb_desc =3D MLX5_MAX_RING_DESC; > hca_attr =3D &priv->sh->cdev->config.hca_attr; > cap->rx_cap.locked_device_memory =3D hca_attr- > >hairpin_data_buffer_locked; > cap->rx_cap.rte_memory =3D 0; > -- > 2.45.2