From: "Xing, Beilei" <beilei.xing@intel.com>
To: "Zhang, Yuying" <yuying.zhang@intel.com>,
"dev@dpdk.org" <dev@dpdk.org>,
"Zhang, Qi Z" <qi.z.zhang@intel.com>,
"Wu, Jingjing" <jingjing.wu@intel.com>
Subject: RE: [PATCH v1 4/5] net/cpfl: add fxp rule module
Date: Fri, 25 Aug 2023 07:35:29 +0000 [thread overview]
Message-ID: <LV2PR11MB599774BCB2ABBB5E32490084F7E3A@LV2PR11MB5997.namprd11.prod.outlook.com> (raw)
In-Reply-To: <20230812075506.361769-5-yuying.zhang@intel.com>
> -----Original Message-----
> From: Zhang, Yuying <yuying.zhang@intel.com>
> Sent: Saturday, August 12, 2023 3:55 PM
> To: dev@dpdk.org; Xing, Beilei <beilei.xing@intel.com>; Zhang, Qi Z
> <qi.z.zhang@intel.com>; Wu, Jingjing <jingjing.wu@intel.com>
> Cc: Zhang, Yuying <yuying.zhang@intel.com>
> Subject: [PATCH v1 4/5] net/cpfl: add fxp rule module
>
> Added low level fxp module for rule packing / creation / destroying.
>
> Signed-off-by: Yuying Zhang <yuying.zhang@intel.com>
> ---
> drivers/net/cpfl/cpfl_ethdev.h | 4 +
> drivers/net/cpfl/cpfl_fxp_rule.c | 288 +++++++++++++++++++++++++++++++
> drivers/net/cpfl/cpfl_fxp_rule.h | 87 ++++++++++
> drivers/net/cpfl/meson.build | 1 +
> 4 files changed, 380 insertions(+)
> create mode 100644 drivers/net/cpfl/cpfl_fxp_rule.c create mode 100644
> drivers/net/cpfl/cpfl_fxp_rule.h
>
> diff --git a/drivers/net/cpfl/cpfl_ethdev.h b/drivers/net/cpfl/cpfl_ethdev.h index
> c71f16ac60..63bcc5551f 100644
> --- a/drivers/net/cpfl/cpfl_ethdev.h
> +++ b/drivers/net/cpfl/cpfl_ethdev.h
> @@ -145,10 +145,14 @@ enum cpfl_itf_type {
>
> TAILQ_HEAD(cpfl_flow_list, rte_flow);
>
> +#define CPFL_FLOW_BATCH_SIZE 490
> struct cpfl_itf {
> enum cpfl_itf_type type;
> struct cpfl_adapter_ext *adapter;
> struct cpfl_flow_list flow_list;
> + struct idpf_dma_mem flow_dma;
> + struct idpf_dma_mem dma[CPFL_FLOW_BATCH_SIZE];
> + struct idpf_ctlq_msg msg[CPFL_FLOW_BATCH_SIZE];
> void *data;
> };
>
> diff --git a/drivers/net/cpfl/cpfl_fxp_rule.c b/drivers/net/cpfl/cpfl_fxp_rule.c
> new file mode 100644
> index 0000000000..936f57e4fa
> --- /dev/null
> +++ b/drivers/net/cpfl/cpfl_fxp_rule.c
> @@ -0,0 +1,288 @@
<...>
> +int
> +cpfl_receive_ctlq_msg(struct idpf_hw *hw, struct idpf_ctlq_info *cq, uint16_t
> num_q_msg,
> + struct idpf_ctlq_msg q_msg[])
> +{
> + int retries = 0;
> + struct idpf_dma_mem *dma;
> + uint16_t i;
> + uint16_t buff_cnt;
> + int ret = 0;
> +
> + retries = 0;
> + while (retries <= CTLQ_RECEIVE_RETRIES) {
> + rte_delay_us_sleep(10);
> + ret = cpfl_vport_ctlq_recv(cq, &num_q_msg, &q_msg[0]);
> +
> + if (ret && ret != CPFL_ERR_CTLQ_NO_WORK &&
> + ret != CPFL_ERR_CTLQ_ERROR) {
> + PMD_INIT_LOG(ERR, "failed to recv ctrlq msg. err:
> 0x%4x\n", ret);
> + retries++;
> + continue;
> + }
> +
> + if (ret == CPFL_ERR_CTLQ_NO_WORK) {
> + retries++;
> + continue;
> + }
> +
> + if (ret == CPFL_ERR_CTLQ_EMPTY)
> + break;
> +
> + ret = cpfl_process_rx_ctlq_msg(num_q_msg, q_msg);
> + if (ret) {
> + PMD_INIT_LOG(WARNING, "failed to process rx_ctrlq
> msg");
> + break;
Don't break, need to post buffer to recv ring.
Please check the internal fix patch.
> + }
> +
> + for (i = 0; i < num_q_msg; i++) {
> + if (q_msg[i].data_len > 0)
> + dma = q_msg[i].ctx.indirect.payload;
> + else
> + dma = NULL;
> +
> + buff_cnt = dma ? 1 : 0;
> + ret = cpfl_vport_ctlq_post_rx_buffs(hw, cq, &buff_cnt,
> &dma);
> + if (ret)
> + PMD_INIT_LOG(WARNING, "could not posted
> recv bufs\n");
> + }
> + break;
> + }
> +
> + if (retries > CTLQ_RECEIVE_RETRIES) {
> + PMD_INIT_LOG(ERR, "timed out while polling for receive
> response");
> + ret = -1;
> + }
> +
> + return ret;
> +}
> +
> +static int
> +pack_mod_rule(struct cpfl_rule_info *rinfo, struct idpf_dma_mem *dma,
Please follow the function name style, how about cpfl_mod_rule_pack?
> + struct idpf_ctlq_msg *msg)
<...>
> +
> +static int pack_default_rule(struct cpfl_rule_info *rinfo, struct idpf_dma_mem
static init
cpfl_default_rule_pack
> *dma,
> + struct idpf_ctlq_msg *msg, bool add) {
<...>
> +
> +static int pack_rule(struct cpfl_rule_info *rinfo, struct idpf_dma_mem *dma,
static init
cpfl_rule_pack
> + struct idpf_ctlq_msg *msg, bool add) {
> + int ret = 0;
> +
> + if (rinfo->type == CPFL_RULE_TYPE_SEM) {
> + if (pack_default_rule(rinfo, dma, msg, add) < 0)
> + ret = -1;
> + } else if (rinfo->type == CPFL_RULE_TYPE_MOD) {
> + if (pack_mod_rule(rinfo, dma, msg) < 0)
> + ret = -1;
> + }
Need to check invalid rinfo->type? E.g CPFL_RULE_TYPE_LEM?
> +
> + return ret;
> +}
> +
> +int
> +cpfl_rule_update(struct cpfl_itf *itf,
> + struct idpf_ctlq_info *tx_cq,
> + struct idpf_ctlq_info *rx_cq,
> + struct cpfl_rule_info *rinfo,
> + int rule_num,
> + bool add)
> +{
> + struct idpf_hw *hw = &itf->adapter->base.hw;
> + int i;
> + int ret = 0;
> +
> + if (rule_num == 0)
> + return 0;
> +
> + for (i = 0; i < rule_num; i++) {
> + ret = pack_rule(&rinfo[i], &itf->dma[i], &itf->msg[i], add);
> + if (ret) {
> + PMD_INIT_LOG(ERR, "Could not create rule");
Could not pack rule?
> + return ret;
> + }
> + }
> + ret = cpfl_send_ctlq_msg(hw, tx_cq, rule_num, itf->msg);
> + if (ret) {
> + PMD_INIT_LOG(ERR, "Failed to send rule");
> + return ret;
> + }
> + ret = cpfl_receive_ctlq_msg(hw, rx_cq, rule_num, itf->msg);
> + if (ret) {
> + PMD_INIT_LOG(ERR, "Failed to create rule");
Is this function for update rule or create rule?
The function name is rule_update, but seems it's to create rule.
> + return ret;
> + }
> +
> + return 0;
> +}
> diff --git a/drivers/net/cpfl/cpfl_fxp_rule.h b/drivers/net/cpfl/cpfl_fxp_rule.h
> new file mode 100644
> index 0000000000..68efa8e3f8
> --- /dev/null
> +++ b/drivers/net/cpfl/cpfl_fxp_rule.h
> @@ -0,0 +1,87 @@
<...>
> +
> +int cpfl_rule_update(struct cpfl_itf *itf,
> + struct idpf_ctlq_info *tx_cq,
> + struct idpf_ctlq_info *rx_cq,
> + struct cpfl_rule_info *rinfo,
> + int rule_num,
> + bool add);
> +int
> +cpfl_send_ctlq_msg(struct idpf_hw *hw, struct idpf_ctlq_info *cq, uint16_t
> num_q_msg,
> + struct idpf_ctlq_msg q_msg[]);
> +int
> +cpfl_receive_ctlq_msg(struct idpf_hw *hw, struct idpf_ctlq_info *cq, uint16_t
> num_q_msg,
No need new line.
> + struct idpf_ctlq_msg q_msg[]);
> +#endif /*CPFL_FXP_RULE_H*/
> diff --git a/drivers/net/cpfl/meson.build b/drivers/net/cpfl/meson.build index
> 222497f7c2..4061123034 100644
> --- a/drivers/net/cpfl/meson.build
> +++ b/drivers/net/cpfl/meson.build
> @@ -46,6 +46,7 @@ if js_dep.found()
> 'cpfl_flow_parser.c',
> 'cpfl_rules.c',
> 'cpfl_controlq.c',
> + 'cpfl_fxp_rule.c',
> )
> dpdk_conf.set('CPFL_FLOW_JSON_SUPPORT', true)
> ext_deps += js_dep
> --
> 2.25.1
next prev parent reply other threads:[~2023-08-25 7:35 UTC|newest]
Thread overview: 128+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-12 7:55 [PATCH v1 0/5] add rte flow support for cpfl Yuying Zhang
2023-08-12 7:55 ` [PATCH v1 1/5] net/cpfl: setup rte flow skeleton Yuying Zhang
2023-08-25 3:55 ` Xing, Beilei
2023-08-12 7:55 ` [PATCH v1 2/5] common/idpf/base: refine idpf ctlq message structure Yuying Zhang
2023-08-25 5:55 ` Xing, Beilei
2023-08-12 7:55 ` [PATCH v1 3/5] net/cpfl: add cpfl control queue message handle Yuying Zhang
2023-08-25 6:23 ` Xing, Beilei
2023-08-12 7:55 ` [PATCH v1 4/5] net/cpfl: add fxp rule module Yuying Zhang
2023-08-25 7:35 ` Xing, Beilei [this message]
2023-08-25 8:42 ` Xing, Beilei
2023-08-12 7:55 ` [PATCH v1 5/5] net/cpfl: add fxp flow engine Yuying Zhang
2023-08-25 9:15 ` Xing, Beilei
2023-09-01 11:31 ` [PATCH v2 0/8] add rte flow support for cpfl Yuying Zhang
2023-09-01 11:31 ` [PATCH v2 1/8] net/cpfl: parse flow parser file in devargs Yuying Zhang
2023-09-01 11:31 ` [PATCH v2 2/8] net/cpfl: add flow json parser Yuying Zhang
2023-09-01 11:31 ` [PATCH v2 3/8] net/cpfl: add FXP low level implementation Yuying Zhang
2023-09-01 11:31 ` [PATCH v2 4/8] net/cpfl: setup ctrl path Yuying Zhang
2023-09-01 11:31 ` [PATCH v2 5/8] net/cpfl: set up rte flow skeleton Yuying Zhang
2023-09-01 11:31 ` [PATCH v2 6/8] net/cpfl: add fxp rule module Yuying Zhang
2023-09-01 11:31 ` [PATCH v2 7/8] net/cpfl: add fxp flow engine Yuying Zhang
2023-09-01 11:31 ` [PATCH v2 8/8] net/cpfl: add flow support for representor Yuying Zhang
2023-09-06 9:33 ` [PATCH v3 0/9] add rte flow support for cpfl Wenjing Qiao
2023-08-15 16:50 ` [PATCH v4 " Zhang, Yuying
2023-08-15 16:50 ` [PATCH v4 1/9] net/cpfl: add json parser for rte flow pattern rules Zhang, Yuying
2023-09-15 15:11 ` Stephen Hemminger
2023-08-15 16:50 ` [PATCH v4 2/9] net/cpfl: add mod rule parser support for rte flow Zhang, Yuying
2023-08-15 16:50 ` [PATCH v4 3/9] net/cpfl: set up rte flow skeleton Zhang, Yuying
2023-08-15 16:50 ` [PATCH v4 4/9] net/cpfl: add FXP low level implementation Zhang, Yuying
2023-08-15 16:50 ` [PATCH v4 5/9] net/cpfl: add fxp rule module Zhang, Yuying
2023-08-15 16:50 ` [PATCH v4 6/9] net/cpfl: add fxp flow engine Zhang, Yuying
2023-08-15 16:50 ` [PATCH v4 7/9] net/cpfl: add flow support for representor Zhang, Yuying
2023-08-15 16:50 ` [PATCH v4 8/9] app/test-pmd: refine encap content Zhang, Yuying
2023-08-15 16:50 ` [PATCH v4 9/9] net/cpfl: fix incorrect status calculation Zhang, Yuying
2023-09-06 9:33 ` [PATCH v3 1/9] net/cpfl: parse flow parser file in devargs Wenjing Qiao
2023-09-11 0:48 ` Wu, Jingjing
2023-09-06 9:34 ` [PATCH v3 2/9] net/cpfl: add flow json parser Wenjing Qiao
2023-09-08 6:26 ` Liu, Mingxia
2023-09-11 6:24 ` Wu, Jingjing
2023-09-06 9:34 ` [PATCH v3 3/9] net/cpfl: add FXP low level implementation Wenjing Qiao
2023-09-06 9:34 ` [PATCH v3 4/9] net/cpfl: setup ctrl path Wenjing Qiao
2023-09-11 6:30 ` Liu, Mingxia
2023-09-11 6:36 ` Wu, Jingjing
2023-09-06 9:34 ` [PATCH v3 5/9] net/cpfl: set up rte flow skeleton Wenjing Qiao
2023-09-06 9:34 ` [PATCH v3 6/9] net/cpfl: add fxp rule module Wenjing Qiao
2023-09-12 7:40 ` FW: " Liu, Mingxia
2023-09-06 9:34 ` [PATCH v3 7/9] net/cpfl: add fxp flow engine Wenjing Qiao
2023-09-06 9:34 ` [PATCH v3 8/9] net/cpfl: add flow support for representor Wenjing Qiao
2023-09-06 9:34 ` [PATCH v3 9/9] app/test-pmd: refine encap content Wenjing Qiao
2023-09-15 10:00 ` [PATCH v5 0/9] add rte flow support for cpfl Zhang, Yuying
2023-08-22 1:02 ` [PATCH v6 0/8] " Zhang, Yuying
2023-08-22 1:02 ` [PATCH v6 1/8] net/cpfl: add json parser for rte flow pattern rules Zhang, Yuying
2023-08-22 1:02 ` [PATCH v6 2/8] net/cpfl: add mod rule parser support for rte flow Zhang, Yuying
2023-08-22 1:02 ` [PATCH v6 3/8] net/cpfl: set up rte flow skeleton Zhang, Yuying
2023-08-22 1:02 ` [PATCH v6 4/8] net/cpfl: set up control path Zhang, Yuying
2023-08-22 1:02 ` [PATCH v6 5/8] net/cpfl: add FXP low level implementation Zhang, Yuying
2023-08-22 1:02 ` [PATCH v6 6/8] net/cpfl: add fxp rule module Zhang, Yuying
2023-08-22 1:02 ` [PATCH v6 7/8] net/cpfl: add fxp flow engine Zhang, Yuying
2023-08-22 1:02 ` [PATCH v6 8/8] net/cpfl: add flow support for representor Zhang, Yuying
2023-09-26 18:16 ` [PATCH v7 0/8] add rte flow support for cpfl yuying.zhang
2023-09-26 18:16 ` [PATCH v7 1/8] net/cpfl: add json parser for rte flow pattern rules yuying.zhang
2023-09-26 19:03 ` Stephen Hemminger
2023-09-27 1:21 ` Zhang, Qi Z
2023-09-26 18:16 ` [PATCH v7 2/8] net/cpfl: build action mapping rules from JSON yuying.zhang
2023-09-26 18:16 ` [PATCH v7 3/8] net/cpfl: set up rte flow skeleton yuying.zhang
2023-09-26 18:16 ` [PATCH v7 4/8] net/cpfl: set up control path yuying.zhang
2023-09-26 18:17 ` [PATCH v7 5/8] net/cpfl: add FXP low level implementation yuying.zhang
2023-09-26 18:17 ` [PATCH v7 6/8] net/cpfl: add fxp rule module yuying.zhang
2023-09-28 3:29 ` Zhang, Qi Z
2023-09-26 18:17 ` [PATCH v7 7/8] net/cpfl: add fxp flow engine yuying.zhang
2023-09-26 18:17 ` [PATCH v7 8/8] net/cpfl: add flow support for representor yuying.zhang
2023-09-27 12:54 ` [PATCH v8 0/9] add rte flow support for cpfl yuying.zhang
2023-09-27 12:54 ` [PATCH v8 1/9] net/cpfl: add json parser for rte flow pattern rules yuying.zhang
2023-09-27 12:54 ` [PATCH v8 2/9] net/cpfl: build action mapping rules from JSON yuying.zhang
2023-09-27 12:54 ` [PATCH v8 3/9] net/cpfl: set up rte flow skeleton yuying.zhang
2023-09-27 12:54 ` [PATCH v8 4/9] net/cpfl: set up control path yuying.zhang
2023-09-27 12:54 ` [PATCH v8 5/9] net/cpfl: add FXP low level implementation yuying.zhang
2023-09-27 12:54 ` [PATCH v8 6/9] net/cpfl: add fxp rule module yuying.zhang
2023-09-27 12:54 ` [PATCH v8 7/9] net/cpfl: add fxp flow engine yuying.zhang
2023-09-27 12:54 ` [PATCH v8 8/9] net/cpfl: add flow support for representor yuying.zhang
2023-09-27 12:54 ` [PATCH v8 9/9] net/cpfl: add support of to represented port action yuying.zhang
2023-09-28 3:37 ` [PATCH v8 0/9] add rte flow support for cpfl Zhang, Qi Z
2023-09-28 8:44 ` [PATCH v9 " yuying.zhang
2023-09-08 16:05 ` [PATCH v10 " Zhang, Yuying
2023-09-08 16:05 ` [PATCH v10 1/9] net/cpfl: parse flow offloading hint from JSON Zhang, Yuying
2023-09-08 16:05 ` [PATCH v10 2/9] net/cpfl: build action mapping rules " Zhang, Yuying
2023-09-08 16:05 ` [PATCH v10 3/9] net/cpfl: set up flow offloading skeleton Zhang, Yuying
2023-09-08 16:05 ` [PATCH v10 4/9] net/cpfl: set up control path Zhang, Yuying
2023-09-08 16:05 ` [PATCH v10 5/9] net/cpfl: add FXP low level implementation Zhang, Yuying
2023-09-08 16:05 ` [PATCH v10 6/9] net/cpfl: implement FXP rule creation and destroying Zhang, Yuying
2023-09-08 16:05 ` [PATCH v10 7/9] net/cpfl: adapt FXP to flow engine Zhang, Yuying
2023-09-08 16:05 ` [PATCH v10 8/9] net/cpfl: support flow ops on representor Zhang, Yuying
2023-09-08 16:05 ` [PATCH v10 9/9] net/cpfl: support represented port action Zhang, Yuying
2023-09-28 8:44 ` [PATCH v9 1/9] net/cpfl: add json parser for rte flow pattern rules yuying.zhang
2023-09-28 8:44 ` [PATCH v9 2/9] net/cpfl: build action mapping rules from JSON yuying.zhang
2023-09-28 8:44 ` [PATCH v9 3/9] net/cpfl: set up rte flow skeleton yuying.zhang
2023-10-15 13:01 ` Thomas Monjalon
2023-10-16 3:07 ` Zhang, Qi Z
2023-09-28 8:44 ` [PATCH v9 4/9] net/cpfl: set up control path yuying.zhang
2023-09-28 8:44 ` [PATCH v9 5/9] net/cpfl: add FXP low level implementation yuying.zhang
2023-09-28 8:44 ` [PATCH v9 6/9] net/cpfl: add fxp rule module yuying.zhang
2023-09-28 8:44 ` [PATCH v9 7/9] net/cpfl: add fxp flow engine yuying.zhang
2023-09-28 8:44 ` [PATCH v9 8/9] net/cpfl: add flow support for representor yuying.zhang
2023-09-28 8:44 ` [PATCH v9 9/9] net/cpfl: add support of to represented port action yuying.zhang
2023-09-28 12:45 ` [PATCH v9 0/9] add rte flow support for cpfl Zhang, Qi Z
2023-09-28 16:04 ` Stephen Hemminger
2023-10-09 4:00 ` [PATCH v10 " Zhang, Yuying
2023-10-09 4:00 ` [PATCH v10 1/9] net/cpfl: parse flow offloading hint from JSON Zhang, Yuying
2023-10-09 4:00 ` [PATCH v10 2/9] net/cpfl: build action mapping rules " Zhang, Yuying
2023-10-09 4:00 ` [PATCH v10 3/9] net/cpfl: set up flow offloading skeleton Zhang, Yuying
2023-10-09 4:00 ` [PATCH v10 4/9] net/cpfl: set up control path Zhang, Yuying
2023-10-09 4:00 ` [PATCH v10 5/9] net/cpfl: add FXP low level implementation Zhang, Yuying
2023-10-09 4:00 ` [PATCH v10 6/9] net/cpfl: implement FXP rule creation and destroying Zhang, Yuying
2023-10-09 4:00 ` [PATCH v10 7/9] net/cpfl: adapt FXP to flow engine Zhang, Yuying
2023-10-09 4:00 ` [PATCH v10 8/9] net/cpfl: support flow ops on representor Zhang, Yuying
2023-10-09 4:00 ` [PATCH v10 9/9] net/cpfl: support represented port action Zhang, Yuying
2023-10-10 1:31 ` [PATCH v10 0/9] add rte flow support for cpfl Zhang, Qi Z
2023-10-15 11:21 ` [PATCH v9 " Thomas Monjalon
2023-09-15 10:00 ` [PATCH v5 1/9] net/cpfl: add json parser for rte flow pattern rules Zhang, Yuying
2023-09-15 11:14 ` Zhang, Qi Z
2023-09-15 10:00 ` [PATCH v5 2/9] net/cpfl: add mod rule parser support for rte flow Zhang, Yuying
2023-09-15 10:00 ` [PATCH v5 3/9] net/cpfl: set up rte flow skeleton Zhang, Yuying
2023-09-15 10:00 ` [PATCH v5 4/9] net/cpfl: add FXP low level implementation Zhang, Yuying
2023-09-15 11:19 ` Zhang, Qi Z
2023-09-15 10:00 ` [PATCH v5 5/9] net/cpfl: add fxp rule module Zhang, Yuying
2023-09-15 10:00 ` [PATCH v5 6/9] net/cpfl: add fxp flow engine Zhang, Yuying
2023-09-15 10:00 ` [PATCH v5 7/9] net/cpfl: add flow support for representor Zhang, Yuying
2023-09-15 10:00 ` [PATCH v5 8/9] app/test-pmd: refine encap content Zhang, Yuying
2023-09-15 10:00 ` [PATCH v5 9/9] net/cpfl: fix incorrect status calculation Zhang, Yuying
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