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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: LV2PR11MB5997.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 13c19943-1965-4420-9da2-08db582bff66 X-MS-Exchange-CrossTenant-originalarrivaltime: 19 May 2023 05:43:39.4417 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: j3CJwjbXxE8XatYq+rUviczlMglXsvXPKIRdgl/P8UlOj45rDMulCc1pBmmO4uJbAMfsxEDD+6r6x0kXFVTLZQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR11MB7437 X-OriginatorOrg: intel.com X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org > -----Original Message----- > From: Liu, Mingxia > Sent: Monday, April 24, 2023 5:48 PM > To: Xing, Beilei ; Wu, Jingjing > Cc: dev@dpdk.org; Wang, Xiao W > Subject: RE: [PATCH 06/10] net/cpfl: support hairpin queue configuration >=20 >=20 >=20 > > -----Original Message----- > > From: Xing, Beilei > > Sent: Friday, April 21, 2023 2:51 PM > > To: Wu, Jingjing > > Cc: dev@dpdk.org; Liu, Mingxia ; Xing, Beilei > > ; Wang, Xiao W > > Subject: [PATCH 06/10] net/cpfl: support hairpin queue configuration > > > > From: Beilei Xing > > > > This patch supports Rx/Tx hairpin queue configuration. > > > > Signed-off-by: Xiao Wang > > Signed-off-by: Mingxia Liu > > Signed-off-by: Beilei Xing > > --- > > drivers/common/idpf/idpf_common_virtchnl.c | 70 +++++++++++ > > drivers/common/idpf/idpf_common_virtchnl.h | 6 + > > drivers/common/idpf/version.map | 2 + > > drivers/net/cpfl/cpfl_ethdev.c | 136 ++++++++++++++++++++- > > drivers/net/cpfl/cpfl_rxtx.c | 80 ++++++++++++ > > drivers/net/cpfl/cpfl_rxtx.h | 7 ++ > > 6 files changed, 297 insertions(+), 4 deletions(-) > > > > diff --git a/drivers/common/idpf/idpf_common_virtchnl.c > > b/drivers/common/idpf/idpf_common_virtchnl.c > > index 76a658bb26..50cd43a8dd 100644 > > --- a/drivers/common/idpf/idpf_common_virtchnl.c > > +++ b/drivers/common/idpf/idpf_common_virtchnl.c <...>=20 > > static int > > cpfl_start_queues(struct rte_eth_dev *dev) { > > + struct cpfl_vport *cpfl_vport =3D dev->data->dev_private; > > + struct idpf_vport *vport =3D &cpfl_vport->base; > > struct cpfl_rx_queue *cpfl_rxq; > > struct cpfl_tx_queue *cpfl_txq; > > + int tx_cmplq_flag =3D 0; > > + int rx_bufq_flag =3D 0; > > + int flag =3D 0; > > int err =3D 0; > > int i; > > > > + /* For normal data queues, configure, init and enale Txq. > > + * For non-cross vport hairpin queues, configure Txq. > > + */ > > for (i =3D 0; i < dev->data->nb_tx_queues; i++) { > > cpfl_txq =3D dev->data->tx_queues[i]; > > if (cpfl_txq =3D=3D NULL || cpfl_txq->base.tx_deferred_start) > > continue; > > - err =3D cpfl_tx_queue_start(dev, i); > > + if (!cpfl_txq->hairpin_info.hairpin_q) { > > + err =3D cpfl_tx_queue_start(dev, i); > > + if (err !=3D 0) { > > + PMD_DRV_LOG(ERR, "Fail to start Tx > > queue %u", i); > > + return err; > > + } > > + } else if (!cpfl_txq->hairpin_info.manual_bind) { > > + if (flag =3D=3D 0) { > > + err =3D cpfl_txq_hairpin_info_update(dev, > > + cpfl_txq- > > >hairpin_info.peer_rxp); > > + if (err !=3D 0) { > > + PMD_DRV_LOG(ERR, "Fail to update > Tx > > hairpin queue info"); > > + return err; > > + } > > + flag =3D 1; > [Liu, Mingxia] The variable flag is not been used, can it be removed? =20 It's used in above code, txq_hairpin_info should be updated once. > > + } > > + err =3D cpfl_hairpin_txq_config(vport, cpfl_txq); > > + if (err !=3D 0) { > > + PMD_DRV_LOG(ERR, "Fail to configure hairpin > > Tx queue %u", i); > > + return err; > > + } > > + tx_cmplq_flag =3D 1; > > + } > > + } > > + >=20 > > + /* For non-cross vport hairpin queues, configure Tx completion queue > > first.*/ > > + if (tx_cmplq_flag =3D=3D 1 && cpfl_vport->p2p_tx_complq !=3D NULL) { > > + err =3D cpfl_hairpin_tx_complq_config(cpfl_vport); > > if (err !=3D 0) { > > - PMD_DRV_LOG(ERR, "Fail to start Tx queue %u", i); > > + PMD_DRV_LOG(ERR, "Fail to config Tx completion > > queue"); > > return err; > > } > > } > > > [Liu, Mingxia] Better to move this code next to > + err =3D cpfl_hairpin_txq_config(vport, cpfl_txq); > + if (err !=3D 0) { > + PMD_DRV_LOG(ERR, "Fail to configure hairpin > Tx queue %u", i); > + return err; > + } > When cpfl_rxq->hairpin_info.hairpin_q is true, then cpfl_vport- > >p2p_tx_complq is not null, right ? > And remove tx_cmplq_flag? Hairpin tx completion queue should only be configured once, so it should no= t be in for loop. However, code is refined in v2. >=20 > > + /* For normal data queues, configure, init and enale Rxq. > > + * For non-cross vport hairpin queues, configure Rxq, and then init R= xq. > > + */ > > + cpfl_rxq_hairpin_mz_bind(dev); > > for (i =3D 0; i < dev->data->nb_rx_queues; i++) { > > cpfl_rxq =3D dev->data->rx_queues[i]; > > if (cpfl_rxq =3D=3D NULL || cpfl_rxq->base.rx_deferred_start) > > continue; > > - err =3D cpfl_rx_queue_start(dev, i); > > + if (!cpfl_rxq->hairpin_info.hairpin_q) { > > + err =3D cpfl_rx_queue_start(dev, i); > > + if (err !=3D 0) { > > + PMD_DRV_LOG(ERR, "Fail to start Rx > > queue %u", i); > > + return err; > > + } > > + } else if (!cpfl_rxq->hairpin_info.manual_bind) { > > + err =3D cpfl_hairpin_rxq_config(vport, cpfl_rxq); > > + if (err !=3D 0) { > > + PMD_DRV_LOG(ERR, "Fail to configure hairpin > > Rx queue %u", i); > > + return err; > > + } > > + err =3D cpfl_rx_queue_init(dev, i); > > + if (err !=3D 0) { > > + PMD_DRV_LOG(ERR, "Fail to init hairpin Rx > > queue %u", i); > > + return err; > > + } > > + rx_bufq_flag =3D 1; > > + } > > + } > > + >=20 > > + /* For non-cross vport hairpin queues, configure Rx buffer queue.*/ > > + if (rx_bufq_flag =3D=3D 1 && cpfl_vport->p2p_rx_bufq !=3D NULL) { > > + err =3D cpfl_hairpin_rx_bufq_config(cpfl_vport); > > if (err !=3D 0) { > > - PMD_DRV_LOG(ERR, "Fail to start Rx queue %u", i); > > + PMD_DRV_LOG(ERR, "Fail to config Rx buffer queue"); > > return err; > > } > > } > [Liu, Mingxia] Similar to above. >=20 > > diff --git a/drivers/net/cpfl/cpfl_rxtx.c > > b/drivers/net/cpfl/cpfl_rxtx.c index 64ed331a6d..040beb5bac 100644 > > --- a/drivers/net/cpfl/cpfl_rxtx.c > > +++ b/drivers/net/cpfl/cpfl_rxtx.c > > @@ -930,6 +930,86 @@ cpfl_tx_hairpin_queue_setup(struct rte_eth_dev > > *dev, uint16_t queue_idx, > > return 0; > > } > > > > +int > > +cpfl_hairpin_rx_bufq_config(struct cpfl_vport *cpfl_vport) { > > + struct idpf_rx_queue *rx_bufq =3D cpfl_vport->p2p_rx_bufq; > > + struct virtchnl2_rxq_info rxq_info[1] =3D {0}; > > + > > + rxq_info[0].type =3D VIRTCHNL2_QUEUE_TYPE_RX_BUFFER; > > + rxq_info[0].queue_id =3D rx_bufq->queue_id; > > + rxq_info[0].ring_len =3D rx_bufq->nb_rx_desc; > > + rxq_info[0].dma_ring_addr =3D rx_bufq->rx_ring_phys_addr; > > + rxq_info[0].desc_ids =3D VIRTCHNL2_RXDID_2_FLEX_SPLITQ_M; > > + rxq_info[0].rx_buffer_low_watermark =3D > > CPFL_RXBUF_LOW_WATERMARK; > > + rxq_info[0].model =3D VIRTCHNL2_QUEUE_MODEL_SPLIT; > > + rxq_info[0].data_buffer_size =3D rx_bufq->rx_buf_len; > > + rxq_info[0].buffer_notif_stride =3D CPFL_RX_BUF_STRIDE; > > + > > + return idpf_vc_rxq_config_by_info(&cpfl_vport->base, rxq_info, 1); } > > + > > +int > > +cpfl_hairpin_rxq_config(struct idpf_vport *vport, struct > > +cpfl_rx_queue > > +*cpfl_rxq) { > > + struct virtchnl2_rxq_info rxq_info[1] =3D {0}; > > + struct idpf_rx_queue *rxq =3D &cpfl_rxq->base; > > + > > + rxq_info[0].type =3D VIRTCHNL2_QUEUE_TYPE_RX; > > + rxq_info[0].queue_id =3D rxq->queue_id; > > + rxq_info[0].ring_len =3D rxq->nb_rx_desc; > > + rxq_info[0].dma_ring_addr =3D rxq->rx_ring_phys_addr; > > + rxq_info[0].rx_bufq1_id =3D rxq->bufq1->queue_id; > > + rxq_info[0].max_pkt_size =3D vport->max_pkt_len; > > + rxq_info[0].desc_ids =3D VIRTCHNL2_RXDID_2_FLEX_SPLITQ_M; > > + rxq_info[0].qflags |=3D VIRTCHNL2_RX_DESC_SIZE_16BYTE; > > + > > + rxq_info[0].data_buffer_size =3D rxq->rx_buf_len; > > + rxq_info[0].model =3D VIRTCHNL2_QUEUE_MODEL_SPLIT; > > + rxq_info[0].rx_buffer_low_watermark =3D > > CPFL_RXBUF_LOW_WATERMARK; > > + > > + PMD_DRV_LOG(NOTICE, "hairpin: vport %u, Rxq id 0x%x", > > + vport->vport_id, rxq_info[0].queue_id); > > + > > + return idpf_vc_rxq_config_by_info(vport, rxq_info, 1); } > > + > > +int > > +cpfl_hairpin_tx_complq_config(struct cpfl_vport *cpfl_vport) { > > + struct idpf_tx_queue *tx_complq =3D cpfl_vport->p2p_tx_complq; > > + struct virtchnl2_txq_info txq_info[1] =3D {0}; > > + > > + txq_info[0].dma_ring_addr =3D tx_complq->tx_ring_phys_addr; > > + txq_info[0].type =3D VIRTCHNL2_QUEUE_TYPE_TX_COMPLETION; > > + txq_info[0].queue_id =3D tx_complq->queue_id; > > + txq_info[0].ring_len =3D tx_complq->nb_tx_desc; > > + txq_info[0].peer_rx_queue_id =3D cpfl_vport->p2p_rx_bufq->queue_id; > > + txq_info[0].model =3D VIRTCHNL2_QUEUE_MODEL_SPLIT; > > + txq_info[0].sched_mode =3D VIRTCHNL2_TXQ_SCHED_MODE_FLOW; > > + > > + return idpf_vc_txq_config_by_info(&cpfl_vport->base, txq_info, 1); } > > + > > +int > > +cpfl_hairpin_txq_config(struct idpf_vport *vport, struct > > +cpfl_tx_queue > > +*cpfl_txq) { > > + struct idpf_tx_queue *txq =3D &cpfl_txq->base; > > + struct virtchnl2_txq_info txq_info[1] =3D {0}; > > + > > + txq_info[0].dma_ring_addr =3D txq->tx_ring_phys_addr; > > + txq_info[0].type =3D VIRTCHNL2_QUEUE_TYPE_TX; > > + txq_info[0].queue_id =3D txq->queue_id; > > + txq_info[0].ring_len =3D txq->nb_tx_desc; > > + txq_info[0].tx_compl_queue_id =3D txq->complq->queue_id; > > + txq_info[0].relative_queue_id =3D txq->queue_id; > > + txq_info[0].peer_rx_queue_id =3D cpfl_txq->hairpin_info.peer_rxq_id; > > + txq_info[0].model =3D VIRTCHNL2_QUEUE_MODEL_SPLIT; > > + txq_info[0].sched_mode =3D VIRTCHNL2_TXQ_SCHED_MODE_FLOW; > > + > > + return idpf_vc_txq_config_by_info(vport, txq_info, 1); } > > + > > int > > cpfl_rx_queue_init(struct rte_eth_dev *dev, uint16_t rx_queue_id) { > > diff --git a/drivers/net/cpfl/cpfl_rxtx.h > > b/drivers/net/cpfl/cpfl_rxtx.h index > > d844c9f057..b01ce5edf9 100644 > > --- a/drivers/net/cpfl/cpfl_rxtx.h > > +++ b/drivers/net/cpfl/cpfl_rxtx.h > > @@ -30,12 +30,15 @@ > > #define CPFL_RING_BASE_ALIGN 128 > > > > #define CPFL_DEFAULT_RX_FREE_THRESH 32 > > +#define CPFL_RXBUF_LOW_WATERMARK 64 > > > > #define CPFL_DEFAULT_TX_RS_THRESH 32 > > #define CPFL_DEFAULT_TX_FREE_THRESH 32 > > > > #define CPFL_SUPPORT_CHAIN_NUM 5 > > > > +#define CPFL_RX_BUF_STRIDE 64 > > + > > struct cpfl_rxq_hairpin_info { > > bool hairpin_q; /* if rx queue is a hairpin queue */ > > bool manual_bind; /* for cross vport */ > > @@ -85,4 +88,8 @@ int cpfl_rx_hairpin_queue_setup(struct rte_eth_dev > > *dev, uint16_t queue_idx, int cpfl_tx_hairpin_queue_setup(struct > > rte_eth_dev *dev, uint16_t queue_idx, > > uint16_t nb_desc, > > const struct rte_eth_hairpin_conf *conf); > > +int cpfl_hairpin_tx_complq_config(struct cpfl_vport *cpfl_vport); int > > +cpfl_hairpin_txq_config(struct idpf_vport *vport, struct > > +cpfl_tx_queue *cpfl_txq); int cpfl_hairpin_rx_bufq_config(struct > > +cpfl_vport *cpfl_vport); int cpfl_hairpin_rxq_config(struct > > +idpf_vport *vport, struct cpfl_rx_queue *cpfl_rxq); > > #endif /* _CPFL_RXTX_H_ */ > > -- > > 2.26.2