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Mon, 15 Mar 2021 17:25:54 +0000 From: "Coyle, David" To: "Lu, Wenzhuo" , "dev@dpdk.org" CC: "Lu, Wenzhuo" , "stable@dpdk.org" Thread-Topic: [dpdk-dev] [PATCH 2/3] net/ice: fix segment fault in AVX512 Thread-Index: AQHXFt8Ah4lQj5wRCUWSvqDND0ZiV6qFTZLg Date: Mon, 15 Mar 2021 17:25:53 +0000 Message-ID: References: <1615512431-17450-1-git-send-email-wenzhuo.lu@intel.com> In-Reply-To: <1615512431-17450-1-git-send-email-wenzhuo.lu@intel.com> Accept-Language: en-IE, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-reaction: no-action dlp-version: 11.5.1.3 dlp-product: dlpe-windows authentication-results: intel.com; dkim=none (message not signed) header.d=none;intel.com; dmarc=none action=none header.from=intel.com; x-originating-ip: [109.78.96.244] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: da5585be-6c64-487d-277e-08d8e7d7633a x-ms-traffictypediagnostic: MN2PR11MB3599: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:4303; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: MN2PR11MB3550.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: da5585be-6c64-487d-277e-08d8e7d7633a X-MS-Exchange-CrossTenant-originalarrivaltime: 15 Mar 2021 17:25:54.0066 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: ULkcxIV9FSsT4xri4uN4fEQ8V3DM3GqDnTONT4Zl66cEdEARgSAn9hS+KaO5JyJhnoBQTxkMKuw4WiPsC9WwaA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR11MB3599 X-OriginatorOrg: intel.com Subject: Re: [dpdk-dev] [PATCH 2/3] net/ice: fix segment fault in AVX512 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Hi Wenzhuo > -----Original Message----- > From: dev On Behalf Of Wenzhuo Lu > Sent: Friday, March 12, 2021 1:27 AM > To: dev@dpdk.org > Cc: Lu, Wenzhuo ; stable@dpdk.org > Subject: [dpdk-dev] [PATCH 2/3] net/ice: fix segment fault in AVX512 >=20 > Fix segment fault when failing to get the memory from the pool. >=20 > Fixes: 7f85d5ebcfe1 ("net/ice: add AVX512 vector path") > Cc: stable@dpdk.org >=20 > Reported-by: David Coyle > Signed-off-by: Wenzhuo Lu > --- > drivers/net/ice/ice_rxtx_vec_avx512.c | 129 > ++++++++++++++++++++++++++++++++++ > 1 file changed, 129 insertions(+) >=20 > diff --git a/drivers/net/ice/ice_rxtx_vec_avx512.c > b/drivers/net/ice/ice_rxtx_vec_avx512.c > index 0e5a676..7c458d5 100644 > --- a/drivers/net/ice/ice_rxtx_vec_avx512.c > +++ b/drivers/net/ice/ice_rxtx_vec_avx512.c > @@ -24,6 +24,9 @@ >=20 > rxdp =3D rxq->rx_ring + rxq->rxrearm_start; >=20 > + if (!cache) > + goto normal; [DC] Same as IAVF, in the Tx path, in ice_tx_free_bufs_avx512(), it also ch= ecks for cache->len =3D=3D 0. Not sure if the extra check is necessary though - I don't know if 'cache' c= an be valid pointer but have a length of 0 if (!cache || cache->len =3D=3D 0) goto normal; > + > /* We need to pull 'n' more MBUFs into the software ring */ > if (cache->len < ICE_RXQ_REARM_THRESH) { > uint32_t req =3D ICE_RXQ_REARM_THRESH + (cache->size - > @@ -115,6 +118,132 @@ > rxep +=3D 8, rxdp +=3D 8, cache->len -=3D 8; > } >=20 > + goto done; > + > +normal: > + /* Pull 'n' more MBUFs into the software ring */ > + if (rte_mempool_get_bulk(rxq->mp, > + (void *)rxep, > + ICE_RXQ_REARM_THRESH) < 0) { > + if (rxq->rxrearm_nb + ICE_RXQ_REARM_THRESH >=3D > + rxq->nb_rx_desc) { > + __m128i dma_addr0; > + > + dma_addr0 =3D _mm_setzero_si128(); > + for (i =3D 0; i < ICE_DESCS_PER_LOOP; i++) { > + rxep[i].mbuf =3D &rxq->fake_mbuf; > + _mm_store_si128((__m128i *)&rxdp[i].read, > + dma_addr0); > + } > + } > + rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed > +=3D > + ICE_RXQ_REARM_THRESH; > + return; > + } > + > +#ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC > + struct rte_mbuf *mb0, *mb1; > + __m128i dma_addr0, dma_addr1; > + __m128i hdr_room =3D _mm_set_epi64x(RTE_PKTMBUF_HEADROOM, > + RTE_PKTMBUF_HEADROOM); > + /* Initialize the mbufs in vector, process 4 mbufs in one loop */ [DC] Comment above should say 2 mbufs > + for (i =3D 0; i < ICE_RXQ_REARM_THRESH; i +=3D 2, rxep +=3D 2) { > + __m128i vaddr0, vaddr1; > + > + mb0 =3D rxep[0].mbuf; > + mb1 =3D rxep[1].mbuf; > + > + /* load buf_addr(lo 64bit) and buf_physaddr(hi 64bit) */ > + RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, buf_iova) !=3D > + offsetof(struct rte_mbuf, buf_addr) + 8); > + vaddr0 =3D _mm_loadu_si128((__m128i *)&mb0->buf_addr); > + vaddr1 =3D _mm_loadu_si128((__m128i *)&mb1->buf_addr); > + > + /* convert pa to dma_addr hdr/data */ > + dma_addr0 =3D _mm_unpackhi_epi64(vaddr0, vaddr0); > + dma_addr1 =3D _mm_unpackhi_epi64(vaddr1, vaddr1); > + > + /* add headroom to pa values */ > + dma_addr0 =3D _mm_add_epi64(dma_addr0, hdr_room); > + dma_addr1 =3D _mm_add_epi64(dma_addr1, hdr_room); > + > + /* flush desc with pa dma_addr */ > + _mm_store_si128((__m128i *)&rxdp++->read, dma_addr0); > + _mm_store_si128((__m128i *)&rxdp++->read, dma_addr1); > + } [DC] As in IAVF, the code above is the same as in avx2 file... any possibil= ity to have a common function or functions for the 2 files? And there is also commonality between IAVF and ICE PMDs. There doesn't seem to be any shared code between net PMDs at the moment tho= ugh, so maybe it's practical to have common functions > +#else > + struct rte_mbuf *mb0, *mb1, *mb2, *mb3; > + struct rte_mbuf *mb4, *mb5, *mb6, *mb7; > + __m512i dma_addr0_3, dma_addr4_7; > + __m512i hdr_room =3D > _mm512_set1_epi64(RTE_PKTMBUF_HEADROOM); > + /* Initialize the mbufs in vector, process 4 mbufs in one loop */ [DC] Comment above should say 8 mbufs > + for (i =3D 0; i < ICE_RXQ_REARM_THRESH; > + i +=3D 8, rxep +=3D 8, rxdp +=3D 8) { > + > + /** > + * merge 0 & 1, by casting 0 to 256-bit and inserting 1 > + * into the high lanes. Similarly for 2 & 3 > + */ [DC] Comment above should say "Similarly for 2 & 3, 4 & 5, 6 & 7" > + vaddr0_1 =3D > + > _mm256_inserti128_si256(_mm256_castsi128_si256(vaddr0), > + vaddr1, 1); > + vaddr2_3 =3D The patch fixes the seg fault, but note I have only tested the default '#if= ndef RTE_LIBRTE_ICE_16BYTE_RX_DESC' path Tested-by: David Coyle