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Fri, 9 Oct 2020 14:04:50 +0000 From: "Coyle, David" To: "Ananyev, Konstantin" , "O'loingsigh, Mairtin" , "Singh, Jasvinder" , "Richardson, Bruce" , "De Lara Guarch, Pablo" CC: "dev@dpdk.org" , "Ryan, Brendan" , "O'loingsigh, Mairtin" Thread-Topic: [dpdk-dev] [PATCH v4 1/2] net: add run-time architecture specific CRC selection Thread-Index: AQHWnLpzlYrW6Lbt2k6qV+pU6h9CCKmPTxUA Date: Fri, 9 Oct 2020 14:04:50 +0000 Message-ID: References: <1601393761-11588-1-git-send-email-mairtin.oloingsigh@intel.com> <20201006162319.7981-1-mairtin.oloingsigh@intel.com> <20201006162319.7981-2-mairtin.oloingsigh@intel.com> In-Reply-To: Accept-Language: en-IE, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-reaction: no-action dlp-version: 11.5.1.3 dlp-product: dlpe-windows authentication-results: intel.com; dkim=none (message not signed) header.d=none;intel.com; dmarc=none action=none header.from=intel.com; x-originating-ip: [109.76.179.29] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: bf19810f-cd32-4e83-f03b-08d86c5c49ef x-ms-traffictypediagnostic: MN2PR11MB4015: x-ld-processed: 46c98d88-e344-4ed4-8496-4ed7712e255d,ExtAddr x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:8882; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: MN2PR11MB3550.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: bf19810f-cd32-4e83-f03b-08d86c5c49ef X-MS-Exchange-CrossTenant-originalarrivaltime: 09 Oct 2020 14:04:50.2769 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: A1B94njrxrDQZIhZU+kAcylbkXYjlv8XWstBtJ7vAa2cQ9teFuBhWjcKHrsUeKO/o5vtELlNjd0HXz8kGuCy4g== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR11MB4015 X-OriginatorOrg: intel.com Subject: Re: [dpdk-dev] [PATCH v4 1/2] net: add run-time architecture specific CRC selection X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Hi Konstantin, thanks for your review > -----Original Message----- > From: Ananyev, Konstantin > Sent: Wednesday, October 7, 2020 3:59 PM >=20 > > > > This patch adds support for run-time selection of the optimal > > architecture-specific CRC path, based on the supported instruction > > set(s) of the CPU. > > > > The compiler option checks have been moved from the C files to the > > meson script. The rte_cpu_get_flag_enabled function is called > > automatically by the library at process initialization time to > > determine which instructions the CPU supports, with the most optimal > > supported CRC path ultimately selected. > > > > Signed-off-by: Mairtin o Loingsigh > > Signed-off-by: David Coyle >=20 > LGTM, just one nit see below. > With that: > Series acked-by: Konstantin Ananyev >=20 > > --- > > doc/guides/rel_notes/release_20_11.rst | 4 ++ > > lib/librte_net/meson.build | 34 +++++++++++- > > lib/librte_net/net_crc.h | 34 ++++++++++++ > > lib/librte_net/{net_crc_neon.h =3D> net_crc_neon.c} | 26 +++------ > > lib/librte_net/{net_crc_sse.h =3D> net_crc_sse.c} | 34 ++++-------- > > lib/librte_net/rte_net_crc.c | 67 ++++++++++++++-= -------- > > 6 files changed, 131 insertions(+), 68 deletions(-) create mode > > 100644 lib/librte_net/net_crc.h rename lib/librte_net/{net_crc_neon.h > > =3D> net_crc_neon.c} (95%) rename lib/librte_net/{net_crc_sse.h =3D> > > net_crc_sse.c} (94%) > > > > > > +#ifdef CC_X86_64_SSE42_PCLMULQDQ_SUPPORT static uint8_t > > +sse42_pclmulqdq_cpu_supported(void) > > +{ > > + return rte_cpu_get_flag_enabled(RTE_CPUFLAG_PCLMULQDQ); > > +} >=20 > As a nit, I think it would be better to hide #fidef inside the function, = and > return an 0 when define is not set. > Something like: >=20 > static int > sse42_pclmulqdq_cpu_supported(void) > { > #ifdef CC_X86_64_SSE42_PCLMULQDQ_SUPPORT > return rte_cpu_get_flag_enabled(RTE_CPUFLAG_PCLMULQDQ); > #else > return 0; > } >=20 > Same for other cpu_supported functions. > And then you can remove these ifdefs in set_alg and other palces, i.e.: >=20 > void > rte_net_crc_set_alg(enum rte_net_crc_alg alg) { > switch (alg) { > #ifdef RTE_ARCH_X86_64 > case RTE_NET_CRC_AVX512: > if (avx512_vpclmulqdq_cpu_supported()) { > handlers =3D handlers_avx512; > break; > } > /* fall-through */ > case RTE_NET_CRC_SSE42: > if (sse42_pclmulqdq_cpu_supported()) { > handlers =3D handlers_sse42; > break; > } > #endif > ... >=20 > Same for rte_net_crc_init() [DC] I have reworked the ifdefs in this file based on your comments here an= d off-list discussions. These are available now in the v5. All ifdef's have been removed out the API function definitions and moved do= wn into 'helper' type functions - looks much cleaner now. Your Ack has been carried through too to v5 as you mentioned >=20 > > +#endif > > + > > +#ifdef CC_ARM64_NEON_PMULL_SUPPORT > > +static uint8_t > > +neon_pmull_cpu_supported(void) > > +{ > > + return rte_cpu_get_flag_enabled(RTE_CPUFLAG_PMULL); > > +} > > +#endif > > + > > void > > rte_net_crc_set_alg(enum rte_net_crc_alg alg) { > > switch (alg) { > > -#ifdef X86_64_SSE42_PCLMULQDQ > > +#ifdef RTE_ARCH_X86_64 > > case RTE_NET_CRC_SSE42: > > - handlers =3D handlers_sse42; > > - break; > > -#elif defined ARM64_NEON_PMULL > > - /* fall-through */ > > +#ifdef CC_X86_64_SSE42_PCLMULQDQ_SUPPORT > > + if (sse42_pclmulqdq_cpu_supported()) { > > + handlers =3D handlers_sse42; > > + break; > > + } > > +#endif > > +#endif /* RTE_ARCH_X86_64 */ > > +#ifdef RTE_ARCH_ARM64 > > case RTE_NET_CRC_NEON: > > - if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_PMULL)) { > > +#ifdef CC_ARM64_NEON_PMULL_SUPPORT > > + if (neon_pmull_cpu_supported()) { > > handlers =3D handlers_neon; > > break; > > } > > #endif > > +#endif /* RTE_ARCH_ARM64 */ > > /* fall-through */ > > case RTE_NET_CRC_SCALAR: > > /* fall-through */ > > @@ -188,11 +200,14 @@ RTE_INIT(rte_net_crc_init) > > > > rte_net_crc_scalar_init(); > > > > -#ifdef X86_64_SSE42_PCLMULQDQ > > - alg =3D RTE_NET_CRC_SSE42; > > - rte_net_crc_sse42_init(); > > -#elif defined ARM64_NEON_PMULL > > - if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_PMULL)) { > > +#ifdef CC_X86_64_SSE42_PCLMULQDQ_SUPPORT > > + if (sse42_pclmulqdq_cpu_supported()) { > > + alg =3D RTE_NET_CRC_SSE42; > > + rte_net_crc_sse42_init(); > > + } > > +#endif > > +#ifdef CC_ARM64_NEON_PMULL_SUPPORT > > + if (neon_pmull_cpu_supported()) { > > alg =3D RTE_NET_CRC_NEON; > > rte_net_crc_neon_init(); > > } > > -- > > 2.12.3