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DIR:OUT; SFP:1102; x-ms-exchange-antispam-messagedata: 7FkShoZXALhQXd/OHtknPkepmMeyc5bHTz2J531l7neewqbztb+QQpSqNjaA2rK/mmjF+YTtzo8Iz4N4Xerzrq6Bzhl63l9r77XcxYXZVEEffUavBQ8yxlKdn8ju+UTmDKmgRy14KrMWGXvsT/+VTePAj76PFeEYYFIVfW4APS1WZRfklew5JEARV568aisTBFrWg8xTmE7GBMj+OwMhMuQs959JaGS4aNU8H4jAyCPJLXpg34ZgwoJCamK7S58aRoJBVFDkzM8DpYaHI3Ahx+6fKym3hqE5E0qfhTqkPJwJIjkS8AGisxy98cyHTMO4tbkfBK5ZZKd0g3/GJRpnw9rJhNugJl4DulHYmSBMz6ZHP6a5ylcqzHaJ1aAVfF4sqvO9M+LLvzM+DLf3JcTypXMqbEe0v2N9MnR+TUGCqYuxluxUhAOPbMOpGyFBm6DHtDfUMmgjG+U3ULgrp71GcZ5V2Zb8bbpp37Otc4aCzsfXqXmkecn9HzWlcuUC0uoT3vTKwm9jyTIYgpTrXWqTqyVaoPSLxXWu9PcjtkZdJ+B7biszCbiLc5CeVi/JZyFrMvJeRq6RQ6Sjn4a5A12WERXgBzja752bvewF6Kxke+W8588M8c0s5424+MV5S89jvpgj3Jc2owmUwXx4sgQqNg== Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: MN2PR11MB3725.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: e97511a5-caac-4011-1051-08d86933e9df X-MS-Exchange-CrossTenant-originalarrivaltime: 05 Oct 2020 13:38:15.8755 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: TItNQj9giPRj0/Vf16h00b5uoRc2aQEHuzdGejpqRXGqbj+DiIPgEayGscOHEhvm9Y8acclD7/J3HcGUhYUqxt5smjTl0qhsGL5bu2t7ODo= X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR11MB4061 X-OriginatorOrg: intel.com Subject: Re: [dpdk-dev] [PATCH v3 2/2] net: add support for AVX512/VPCLMULQDQ based CRC X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Hi Pablo, > -----Original Message----- > From: De Lara Guarch, Pablo > Sent: Monday, October 5, 2020 2:20 PM > To: O'loingsigh, Mairtin ; Singh, Jasvinder > ; Richardson, Bruce > > Cc: dev@dpdk.org; Ryan, Brendan ; Coyle, David > > Subject: RE: [PATCH v3 2/2] net: add support for AVX512/VPCLMULQDQ > based CRC >=20 > Hi Mairtin, >=20 > > -----Original Message----- > > From: O'loingsigh, Mairtin > > Sent: Tuesday, September 29, 2020 4:36 PM > > To: Singh, Jasvinder ; Richardson, Bruce > > ; De Lara Guarch, Pablo > > > > Cc: dev@dpdk.org; Ryan, Brendan ; Coyle, > David > > ; O'loingsigh, Mairtin > > > > Subject: [PATCH v3 2/2] net: add support for AVX512/VPCLMULQDQ based > > CRC > > > > This patch enables the optimized calculation of CRC32-Ethernet and > > CRC16- CCITT using the AVX512 and VPCLMULQDQ instruction sets. This > > CRC implementation is built if the compiler supports the required > > instruction sets. It is selected at run-time if the host CPU, again, > > supports the required instruction sets. > > > > Signed-off-by: Mairtin o Loingsigh > > Signed-off-by: David Coyle >=20 > ... >=20 > > +static __rte_always_inline uint32_t > > +crc32_eth_calc_vpclmulqdq(const uint8_t *data, uint32_t data_len, > > +uint32_t > > crc, > > + const struct crc_vpclmulqdq_ctx *params) { > > + __m128i res, d; > > + __m256i b; > > + __m512i temp, k; > > + __m512i qw0 =3D _mm512_set1_epi64(0), qw1, qw2, qw3; > > + __m512i fold0, fold1, fold2, fold3; > > + __mmask16 mask; > > + uint32_t n =3D 0; > > + int reduction =3D 0; > > + > > + /* Get CRC init value */ > > + b =3D _mm256_insert_epi32(_mm256_setzero_si256(), crc, 0); > > + temp =3D _mm512_inserti32x8(_mm512_setzero_si512(), b, 0); >=20 > You can replace this with the following, which produces less instructions= (b > needs to be changed to __m128i): >=20 > b =3D _mm_cvtsi32_si128(crc); > temp =3D _mm512_castsi128_si512(b); >=20 > > + > > + if (data_len > 255) { > > + fold0 =3D _mm512_loadu_si512((const __m512i *)data); >=20 > ... >=20 > > + } else { > > + if (data_len > 31) { > > + res =3D _mm_insert_epi32(_mm_setzero_si128(), crc, > 0); >=20 > Should work better with: >=20 > res =3D _mm_cvtsi32_si128(crc); >=20 > > + d =3D _mm_loadu_si128((const __m128i *)data); > > + res =3D _mm_xor_si128(res, d); > > + n +=3D 16; > > + > > + reduction =3D 240 - ((n+256)-data_len); > > + > > + while (reduction > 0) > > + reduction_loop(&res, &reduction, data, &n, > > + params); > > + > > + if (n !=3D data_len) > > + res =3D last_two_xmm(data, data_len, n, res, > > + params); > > + } else if (data_len > 16) { > > + res =3D _mm_insert_epi32(_mm_setzero_si128(), crc, > 0); >=20 > Same as above. >=20 > > + d =3D _mm_loadu_si128((const __m128i *)data); > > + res =3D _mm_xor_si128(res, d); > > + n +=3D 16; > > + > > + if (n !=3D data_len) > > + res =3D last_two_xmm(data, data_len, n, res, > > + params); > > + } else if (data_len =3D=3D 16) { > > + res =3D _mm_insert_epi32(_mm_setzero_si128(), crc, > 0); >=20 > Same. >=20 > > + d =3D _mm_loadu_si128((const __m128i *)data); > > + res =3D _mm_xor_si128(res, d); > > + } else { > > + res =3D _mm_insert_epi32(_mm_setzero_si128(), crc, > 0); >=20 > Same. >=20 > > + mask =3D byte_len_to_mask_table[data_len]; > > + d =3D _mm_maskz_loadu_epi8(mask, data); Thanks for the feedback. Ill make these changes and submit a v4 patch Regards, Mairtin