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DIR:OUT; SFP:1102; x-ms-exchange-antispam-messagedata: 4HMsw1T0dEt/yCYv78xBUUVUt2YtuWAj+fZhGdA2tQom3vIdFm0lSuMxdljhTSbXj2C67qwnAlG5r8nTGiCPbgkzg5K1k9GSwDjlbNSAe2HODJpDhcHhTjaiHSLAcvDLVxc3RNMaJtPZEoZzpd8TUSoNPnlGlGmLyveLdUS1YOAioJxWYEc3wQvrj3+O+s5FDTk27mQk9VAotpHs1MTGSftTLuXeAt+CTu4ftCoL6zIesZZgFs6OQTFv60HgCBGb2qJaZAHzk6VnH6vN491dsrfV0L3zev8IM59sKqJHlBlbYUujda/llTPh9GkypHbyQhQgwiC4OhHQp0Uq0e4bSniyIzkI9fVuf3rNo5oq4wH41VhqZPvzOixiRG/ukD3KYewMEQAWoOjDUlJAjvn3zOvBMEcr0qYLRdYS/CzORG96oPEkDtyul1PWIapEEZO03xPrUp4UzaDO6F7FwP6AUQj73vSkXvZG0lYElj3HDNchDWy5fqGYzcxsJF/73WxpJNZWE3Vz/C/L1ASWH+S6TcmeBLK/+I8drmr0JlCvxwc0wfTb+OYes1goB9+q5VMAwRj2+/BnuYJ4kQv/1W4xB6VNKKdqMGzK8KZS8kA1CS8Zun9/XzWS2ZJkEmo/MdsGdid30+3SXclCLphz5NcvZg== Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: MN2PR11MB3725.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 57c531e8-d9e7-4544-b858-08d86a1647f0 X-MS-Exchange-CrossTenant-originalarrivaltime: 06 Oct 2020 16:38:40.0338 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 8e8Ivbv59JkhQ5EawP/R4jlGKpc0XDgAE3NDSgzGNGPTqHrmw3p+FTnMth0JbVX5UVsUWuc3+kFVoidnAP3YWAdKYocPHmbTJIROevXvuRg= X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR11MB3837 X-OriginatorOrg: intel.com Subject: Re: [dpdk-dev] [PATCH v3 1/2] net: add run-time architecture specific CRC selection X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Hi, > -----Original Message----- > From: Singh, Jasvinder > Sent: Friday, October 2, 2020 4:18 PM > To: O'loingsigh, Mairtin ; Richardson, Bruc= e > ; De Lara Guarch, Pablo > > Cc: dev@dpdk.org; Ryan, Brendan ; Coyle, David > > Subject: RE: [PATCH v3 1/2] net: add run-time architecture specific CRC > selection >=20 >=20 >=20 > > -----Original Message----- > > From: O'loingsigh, Mairtin > > Sent: Tuesday, September 29, 2020 4:36 PM > > To: Singh, Jasvinder ; Richardson, Bruce > > ; De Lara Guarch, Pablo > > > > Cc: dev@dpdk.org; Ryan, Brendan ; Coyle, > David > > ; O'loingsigh, Mairtin > > > > Subject: [PATCH v3 1/2] net: add run-time architecture specific CRC > > selection > > > > This patch adds support for run-time selection of the optimal > > architecture- specific CRC path, based on the supported instruction set= (s) > of the CPU. > > > > The compiler option checks have been moved from the C files to the > > meson script. The rte_cpu_get_flag_enabled function is called > > automatically by the library at process initialization time to > > determine which instructions the CPU supports, with the most optimal > supported CRC path ultimately selected. > > > > Signed-off-by: Mairtin o Loingsigh > > Signed-off-by: David Coyle > > --- > > doc/guides/rel_notes/release_20_11.rst | 4 ++ > > lib/librte_net/meson.build | 34 +++++++++++- > > lib/librte_net/net_crc.h | 34 ++++++++++++ > > lib/librte_net/{net_crc_neon.h =3D> net_crc_neon.c} | 27 +++------ > > lib/librte_net/{net_crc_sse.h =3D> net_crc_sse.c} | 34 ++++-------- > > lib/librte_net/rte_net_crc.c | 67 ++++++++++++++-= -------- > > 6 files changed, 132 insertions(+), 68 deletions(-) create mode > > 100644 lib/librte_net/net_crc.h rename lib/librte_net/{net_crc_neon.h > > =3D> net_crc_neon.c} (95%) rename lib/librte_net/{net_crc_sse.h =3D> > > net_crc_sse.c} (94%) > > > > diff --git a/doc/guides/rel_notes/release_20_11.rst > > b/doc/guides/rel_notes/release_20_11.rst > > index 4eb3224a7..6bd222dca 100644 > > --- a/doc/guides/rel_notes/release_20_11.rst > > +++ b/doc/guides/rel_notes/release_20_11.rst > > @@ -55,6 +55,10 @@ New Features > > Also, make sure to start the actual text at the margin. > > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D >=20 > >=20 >=20 > _t *data, uint32_t data_len); > > + > > +#endif /* _NET_CRC_H_ */ > > diff --git a/lib/librte_net/net_crc_neon.h > > b/lib/librte_net/net_crc_neon.c similarity index 95% rename from > > lib/librte_net/net_crc_neon.h rename to lib/librte_net/net_crc_neon.c > > index 63fa1d4a1..b79684ec2 100644 > > --- a/lib/librte_net/net_crc_neon.h > > +++ b/lib/librte_net/net_crc_neon.c > > @@ -1,18 +1,17 @@ > > /* SPDX-License-Identifier: BSD-3-Clause > > * Copyright(c) 2017 Cavium, Inc > > + * Copyright(c) 2020 Intel Corporation > > */ >=20 > Could you please remove intel copyright as there is no change in this fil= e? >=20 > > -#ifndef _NET_CRC_NEON_H_ > > -#define _NET_CRC_NEON_H_ > > +#include > > > > +#include > > #include > > #include > > #include > > #include > > > > -#ifdef __cplusplus > > -extern "C" { > > -#endif > > +#include "net_crc.h" > > > > /** PMULL CRC computation context structure */ struct crc_pmull_ctx > > { @@ > > -218,7 +217,7 @@ crc32_eth_calc_pmull( > > return n; > > } > > > > -static inline void > > +void > > rte_net_crc_neon_init(void) > > { > > /* Initialize CRC16 data */ > > @@ -242,9 +241,8 @@ rte_net_crc_neon_init(void) > > crc32_eth_pmull.rk7_rk8 =3D vld1q_u64(eth_k7_k8); } > > > > -static inline uint32_t > > -rte_crc16_ccitt_neon_handler(const uint8_t *data, > > - uint32_t data_len) > > +uint32_t > > +rte_crc16_ccitt_neon_handler(const uint8_t *data, uint32_t data_len) > > { > > return (uint16_t)~crc32_eth_calc_pmull(data, > > data_len, > > @@ -252,18 +250,11 @@ rte_crc16_ccitt_neon_handler(const uint8_t > *data, > > &crc16_ccitt_pmull); > > } > > > > -static inline uint32_t > > -rte_crc32_eth_neon_handler(const uint8_t *data, > > - uint32_t data_len) > > +uint32_t > > +rte_crc32_eth_neon_handler(const uint8_t *data, uint32_t data_len) > > { > > return ~crc32_eth_calc_pmull(data, > > data_len, > > 0xffffffffUL, > > &crc32_eth_pmull); > > } > > - > > -#ifdef __cplusplus > > -} > > -#endif > > - > > -#endif /* _NET_CRC_NEON_H_ */ > > diff --git a/lib/librte_net/net_crc_sse.h > > b/lib/librte_net/net_crc_sse.c similarity index 94% rename from > > lib/librte_net/net_crc_sse.h rename to lib/librte_net/net_crc_sse.c > > index 1c7b7a548..053b54b39 100644 > > --- a/lib/librte_net/net_crc_sse.h > > +++ b/lib/librte_net/net_crc_sse.c > > @@ -1,18 +1,16 @@ > > /* SPDX-License-Identifier: BSD-3-Clause > > - * Copyright(c) 2017 Intel Corporation > > + * Copyright(c) 2017-2020 Intel Corporation > > */ > > > > -#ifndef _RTE_NET_CRC_SSE_H_ > > -#define _RTE_NET_CRC_SSE_H_ > > +#include > > > > +#include > > #include > > +#include > > > > -#include > > -#include > > +#include "net_crc.h" > > > > -#ifdef __cplusplus > > -extern "C" { > > -#endif > > +#include > > > > /** PCLMULQDQ CRC computation context structure */ struct > > crc_pclmulqdq_ctx { @@ -259,8 +257,7 @@ crc32_eth_calc_pclmulqdq( > > return n; > > } > > > > - > > -static inline void > > +void > > rte_net_crc_sse42_init(void) > > { > > uint64_t k1, k2, k5, k6; > > @@ -303,12 +300,10 @@ rte_net_crc_sse42_init(void) > > * use other data types such as float, double, etc. > > */ > > _mm_empty(); > > - > > } > > > > -static inline uint32_t > > -rte_crc16_ccitt_sse42_handler(const uint8_t *data, > > - uint32_t data_len) > > +uint32_t > > +rte_crc16_ccitt_sse42_handler(const uint8_t *data, uint32_t data_len) > > { > > /** return 16-bit CRC value */ > > return (uint16_t)~crc32_eth_calc_pclmulqdq(data, > > @@ -317,18 +312,11 @@ rte_crc16_ccitt_sse42_handler(const uint8_t > > *data, > > &crc16_ccitt_pclmulqdq); > > } > > > > -static inline uint32_t > > -rte_crc32_eth_sse42_handler(const uint8_t *data, > > - uint32_t data_len) > > +uint32_t > > +rte_crc32_eth_sse42_handler(const uint8_t *data, uint32_t data_len) > > { > > return ~crc32_eth_calc_pclmulqdq(data, > > data_len, > > 0xffffffffUL, > > &crc32_eth_pclmulqdq); > > } > > - > > -#ifdef __cplusplus > > -} > > -#endif > > - > > -#endif /* _RTE_NET_CRC_SSE_H_ */ > > diff --git a/lib/librte_net/rte_net_crc.c > > b/lib/librte_net/rte_net_crc.c index 4f5b9e828..83dccbfba 100644 > > --- a/lib/librte_net/rte_net_crc.c > > +++ b/lib/librte_net/rte_net_crc.c > > @@ -1,5 +1,5 @@ > > /* SPDX-License-Identifier: BSD-3-Clause > > - * Copyright(c) 2017 Intel Corporation > > + * Copyright(c) 2017-2020 Intel Corporation > > */ > > > > #include > > @@ -10,17 +10,7 @@ > > #include > > #include > > > > -#if defined(RTE_ARCH_X86_64) && defined(__PCLMUL__) > > -#define X86_64_SSE42_PCLMULQDQ 1 > > -#elif defined(RTE_ARCH_ARM64) && defined(__ARM_FEATURE_CRYPTO) > > -#define ARM64_NEON_PMULL 1 > > -#endif > > - > > -#ifdef X86_64_SSE42_PCLMULQDQ > > -#include > > -#elif defined ARM64_NEON_PMULL > > -#include > > -#endif > > +#include "net_crc.h" > > > > /** CRC polynomials */ > > #define CRC32_ETH_POLYNOMIAL 0x04c11db7UL @@ -47,13 +37,13 @@ > static > > rte_net_crc_handler handlers_scalar[] =3D { > > [RTE_NET_CRC16_CCITT] =3D rte_crc16_ccitt_handler, > > [RTE_NET_CRC32_ETH] =3D rte_crc32_eth_handler, }; > > - > > -#ifdef X86_64_SSE42_PCLMULQDQ > > +#ifdef CC_X86_64_SSE42_PCLMULQDQ_SUPPORT > > static rte_net_crc_handler handlers_sse42[] =3D { > > [RTE_NET_CRC16_CCITT] =3D rte_crc16_ccitt_sse42_handler, > > [RTE_NET_CRC32_ETH] =3D rte_crc32_eth_sse42_handler, }; -#elif > > defined ARM64_NEON_PMULL > > +#endif > > +#ifdef CC_ARM64_NEON_PMULL_SUPPORT > > static rte_net_crc_handler handlers_neon[] =3D { > > [RTE_NET_CRC16_CCITT] =3D rte_crc16_ccitt_neon_handler, > > [RTE_NET_CRC32_ETH] =3D rte_crc32_eth_neon_handler, @@ -142,22 > > +132,44 @@ rte_crc32_eth_handler(const uint8_t *data, uint32_t > > +data_len) > > crc32_eth_lut); > > } > > > > +#ifdef CC_X86_64_SSE42_PCLMULQDQ_SUPPORT static uint8_t > > +sse42_pclmulqdq_cpu_supported(void) > > +{ > > + return rte_cpu_get_flag_enabled(RTE_CPUFLAG_PCLMULQDQ); > > +} > > +#endif > > + > > +#ifdef CC_ARM64_NEON_PMULL_SUPPORT > > +static uint8_t > > +neon_pmull_cpu_supported(void) > > +{ > > + return rte_cpu_get_flag_enabled(RTE_CPUFLAG_PMULL); > > +} > > +#endif > > + > > void > > rte_net_crc_set_alg(enum rte_net_crc_alg alg) { > > switch (alg) { > > -#ifdef X86_64_SSE42_PCLMULQDQ > > +#ifdef RTE_ARCH_X86_64 > > case RTE_NET_CRC_SSE42: > > - handlers =3D handlers_sse42; > > - break; > > -#elif defined ARM64_NEON_PMULL > > - /* fall-through */ > > +#ifdef CC_X86_64_SSE42_PCLMULQDQ_SUPPORT > > + if (sse42_pclmulqdq_cpu_supported()) { > > + handlers =3D handlers_sse42; > > + break; > > + } > > +#endif > > +#endif /* RTE_ARCH_X86_64 */ > > +#ifdef RTE_ARCH_ARM64 > > case RTE_NET_CRC_NEON: > > - if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_PMULL)) { > > +#ifdef CC_ARM64_NEON_PMULL_SUPPORT > > + if (neon_pmull_cpu_supported()) { > > handlers =3D handlers_neon; > > break; > > } > > #endif > > +#endif /* RTE_ARCH_ARM64 */ > > /* fall-through */ > > case RTE_NET_CRC_SCALAR: > > /* fall-through */ > > @@ -188,11 +200,14 @@ RTE_INIT(rte_net_crc_init) > > > > rte_net_crc_scalar_init(); > > > > -#ifdef X86_64_SSE42_PCLMULQDQ > > - alg =3D RTE_NET_CRC_SSE42; > > - rte_net_crc_sse42_init(); > > -#elif defined ARM64_NEON_PMULL > > - if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_PMULL)) { > > +#ifdef CC_X86_64_SSE42_PCLMULQDQ_SUPPORT > > + if (sse42_pclmulqdq_cpu_supported()) { > > + alg =3D RTE_NET_CRC_SSE42; > > + rte_net_crc_sse42_init(); > > + } > > +#endif > > +#ifdef CC_ARM64_NEON_PMULL_SUPPORT > > + if (neon_pmull_cpu_supported()) { > > alg =3D RTE_NET_CRC_NEON; > > rte_net_crc_neon_init(); > > } > > -- > > 2.12.3 >=20 > Patch looks good to me except the one stated above. >=20 >=20 Fix for above comment on copyright has been applied to v4 patch which was j= ust submitted Regards, Mairtin