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Tue, 29 Sep 2020 15:47:25 +0000 From: "O'loingsigh, Mairtin" To: "De Lara Guarch, Pablo" , "Singh, Jasvinder" CC: "dev@dpdk.org" , "Ryan, Brendan" , "Coyle, David" Thread-Topic: [PATCH] net: add support for AVX512 when generating CRC Thread-Index: AQHWh2ot3PVCYcPcP0qhNCI3WD6U96ljNTiAgByrEBA= Date: Tue, 29 Sep 2020 15:47:25 +0000 Message-ID: References: <1599739271-16605-1-git-send-email-mairtin.oloingsigh@intel.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-reaction: no-action dlp-version: 11.5.1.3 authentication-results: intel.com; dkim=none (message not signed) header.d=none;intel.com; dmarc=none action=none header.from=intel.com; x-originating-ip: [86.44.213.168] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 463711cb-1fc5-490d-2bd5-08d8648ef6ae x-ms-traffictypediagnostic: MN2PR11MB4693: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:7691; 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SFP:1102; x-ms-exchange-antispam-messagedata: b46vT8PggEzGeFopk1DNQu8piJeutOur6Wav+1OjtXR7DRtWVA0EHDxBXgZLianbT9lrGT52YEd53d4XO15dyZDyG/1jS7dtSofJbaCqhhbaDfBoCjydFIEgyeFuDuzncu3Hb5EcRaAOAJm5GHIMsPKj4+9bTZ8Nbg+fJ5rCZ+xJfF2L356msUISuIZZuXjUGGO0XTmbnr472/DVSIqlgynMitJwMeyIZpkSWMVV/omhI773QCCqIGvzYIaegkcAKHlqrfKV7o4bAy9//OVuO35agUiCqNb2YCV3admkYLotnx7t8s+gmymQVrEaOPYK0GJGppKVMIPratCyhMVMHyAbCGX4DXtUMXceIiSUP46OMrPpvlIsubzkQWYJ32J3BXZ0ocxmp9O2vTErD+0e5n0yRfa40uwkL+lWyKwaiADkzOBUCeB+SiZNYTBuaEKwlhpDST1kL9owDozDeS3ygi/+fBQZV1AMEgWKv0g/Y36wGbg0VHeeMFhkQPd8iuYM3r/GHGPzQp1C5RpFx/ZLDM1HMck0HgAQHeTaQ5AUGqj6FR5xagLl4dOEZaxBN+lQChtJe2EyjGRcF5yOgnEgzZNoy9tk821pSM9Y32AIGf655a0EJKgN4wcljXGna40pWADJRcrkV5rWV57l2mJTKQ== Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: MN2PR11MB3725.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 463711cb-1fc5-490d-2bd5-08d8648ef6ae X-MS-Exchange-CrossTenant-originalarrivaltime: 29 Sep 2020 15:47:25.8449 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: SQUpa+a1QD/4Oyg8gNWbRgXhkMT08HH4JCBOfDHgimksoHRmofzphwBwnyBtIEIQ3v6QAGe2iv/e4nOCM1hnDCLtbbXoZWELcxl7TO6Eib4= X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR11MB4693 X-OriginatorOrg: intel.com Subject: Re: [dpdk-dev] [PATCH] net: add support for AVX512 when generating CRC X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Hi, > -----Original Message----- > From: De Lara Guarch, Pablo > Sent: Friday, September 11, 2020 10:58 AM > To: O'loingsigh, Mairtin ; Singh, Jasvinder > > Cc: dev@dpdk.org; Ryan, Brendan ; Coyle, David > > Subject: RE: [PATCH] net: add support for AVX512 when generating CRC >=20 > Hi Mairtin, >=20 > > -----Original Message----- > > From: O'loingsigh, Mairtin > > Sent: Thursday, September 10, 2020 1:01 PM > > To: Singh, Jasvinder > > Cc: dev@dpdk.org; Ryan, Brendan ; Coyle, > David > > ; De Lara Guarch, Pablo > > ; O'loingsigh, Mairtin > > > > Subject: [PATCH] net: add support for AVX512 when generating CRC > > > > This patch enables the generation of CRC using AVX512 instruction set > > when available on the host platform. > > > > Signed-off-by: Mairtin o Loingsigh > > --- > > > > v1: > > * Initial version, with AVX512 support for CRC32 Ethernet only > > (requires further > > updates) > > * AVX512 support for CRC16-CCITT and final implementation of > > CRC32 Ethernet will be added in v2 > > --- > > doc/guides/rel_notes/release_20_11.rst | 4 + > > lib/librte_net/net_crc_avx.h | 331 > ++++++++++++++++++++++++++++++++ > > lib/librte_net/rte_net_crc.c | 23 ++- > > lib/librte_net/rte_net_crc.h | 1 + > > 4 files changed, 358 insertions(+), 1 deletions(-) create mode > > 100644 lib/librte_net/net_crc_avx.h > > > > diff --git a/doc/guides/rel_notes/release_20_11.rst > > b/doc/guides/rel_notes/release_20_11.rst > > index df227a1..d6a84ca 100644 > > --- a/doc/guides/rel_notes/release_20_11.rst > > +++ b/doc/guides/rel_notes/release_20_11.rst > > @@ -55,6 +55,10 @@ New Features > > Also, make sure to start the actual text at the margin. > > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D > > > > +* **Added support for AVX512 in rte_net CRC calculations.** > > + > > + Added new CRC32 calculation code using AVX512 instruction set > > + Added new CRC16-CCITT calculation code using AVX512 instruction set > > > > Removed Items > > ------------- > > diff --git a/lib/librte_net/net_crc_avx.h > > b/lib/librte_net/net_crc_avx.h new file mode 100644 index > > 0000000..d9481d5 > > --- /dev/null > > +++ b/lib/librte_net/net_crc_avx.h >=20 > ... >=20 > > +static __rte_always_inline uint32_t > > +crc32_eth_calc_pclmulqdq( > > + const uint8_t *data, > > + uint32_t data_len, > > + uint32_t crc, > > + const struct crc_pclmulqdq512_ctx *params) { > > + __m256i b; > > + __m512i temp, k; > > + __m512i qw0 =3D _mm512_set1_epi64(0); > > + __m512i fold0; > > + uint32_t n; >=20 > This is loading 64 bytes of data, but if seems like only 16 are available= , right? > Should we use _mm_loadu_si128? >=20 > > + fold0 =3D _mm512_xor_si512(fold0, temp); > > + goto reduction_128_64; > > + } > > + > > + if (unlikely(data_len < 16)) { > > + /* 0 to 15 bytes */ > > + uint8_t buffer[16] __rte_aligned(16); > > + > > + memset(buffer, 0, sizeof(buffer)); > > + memcpy(buffer, data, data_len); >=20 > I would use _mm_maskz_loadu_epi8, passing a mask register with ((1 << > data_len) - 1). >=20 > > + > > + fold0 =3D _mm512_load_si512((const __m128i > *)buffer); > > + fold0 =3D _mm512_xor_si512(fold0, temp); > > + if (unlikely(data_len < 4)) { > > + fold0 =3D xmm_shift_left(fold0, 8 - data_len); > > + goto barret_reduction; > > + } > > + fold0 =3D xmm_shift_left(fold0, 16 - data_len); > > + goto reduction_128_64; > > + } > > + /* 17 to 31 bytes */ > > + fold0 =3D _mm512_loadu_si512((const __m512i *)data); >=20 > Same here. Looks like you are loading too much data? >=20 > > + fold0 =3D _mm512_xor_si512(fold0, temp); > > + n =3D 16; > > + k =3D params->rk1_rk2; > > + goto partial_bytes; > > + } >=20 > ... >=20 > > + > > + fold0 =3D _mm512_xor_si512(fold0, temp); > > + fold0 =3D _mm512_xor_si512(fold0, b); >=20 > You could use _mm512_ternarylogic_epi64 with 0x96 as to do 2x XORs in one > instruction. >=20 > > + } > > + > > + /** Reduction 128 -> 32 Assumes: fold holds 128bit folded data */ > > +reduction_128_64: > > + k =3D params->rk5_rk6; > > + > > +barret_reduction: > > + k =3D params->rk7_rk8; > > + n =3D crcr32_reduce_64_to_32(fold0, k); > > + > > + return n; > > +} > > + > > + The latest version of this patch (v3) reworks a lot of this code and addres= s the issues noted above Mairtin