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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: MN2PR11MB3807.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: a2715376-89e1-4f11-5907-08d93b948d1f X-MS-Exchange-CrossTenant-originalarrivaltime: 30 Jun 2021 06:59:05.6877 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: /AjotJljLnXL1bjjzY/8zWcwz/bdbXeNY9CYM6QtbEL70RJ76OUVzt7VNOvKWvhDBZNiu7TE9XW6UKIwUvZpHQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR11MB4693 X-OriginatorOrg: intel.com Subject: Re: [dpdk-dev] [PATCH v3 1/2] net/i40e: improve performance for scalar Tx X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: Feifei Wang > Sent: Wednesday, June 30, 2021 2:41 PM > To: Xing, Beilei > Cc: dev@dpdk.org; nd@arm.com; Feifei Wang ; > Ruifeng Wang > Subject: [PATCH v3 1/2] net/i40e: improve performance for scalar Tx >=20 > For i40e scalar Tx path, if implement FAST_FREE_MBUF mode, it means per- > queue all mbufs come from the same mempool and have refcnt =3D 1. >=20 > Thus we can use bulk free of the buffers when mbuf fast free mode is > enabled. >=20 > Following are the test results with this patch: >=20 > MRR L3FWD Test: > two ports & bi-directional flows & one core RX API: > i40e_recv_pkts_bulk_alloc TX API: i40e_xmit_pkts_simple ring_descs_size = =3D > 1024; Ring_I40E_TX_MAX_FREE_SZ =3D 64; tx_rs_thresh =3D > I40E_DEFAULT_TX_RSBIT_THRESH =3D 32; tx_free_thresh =3D > I40E_DEFAULT_TX_FREE_THRESH =3D 32; >=20 > For scalar path in arm platform with default 'tx_rs_thresh': > In n1sdp, performance is improved by 7.9%; In thunderx2, performance is > improved by 7.6%. >=20 > For scalar path in x86 platform with default 'tx_rs_thresh': > performance is improved by 4.7%. >=20 > Suggested-by: Ruifeng Wang > Signed-off-by: Feifei Wang > Reviewed-by: Ruifeng Wang > --- > drivers/net/i40e/i40e_rxtx.c | 30 ++++++++++++++++++++++++------ > 1 file changed, 24 insertions(+), 6 deletions(-) >=20 > diff --git a/drivers/net/i40e/i40e_rxtx.c b/drivers/net/i40e/i40e_rxtx.c = index > 6c58decece..0d3482a9d2 100644 > --- a/drivers/net/i40e/i40e_rxtx.c > +++ b/drivers/net/i40e/i40e_rxtx.c > @@ -1294,22 +1294,40 @@ static __rte_always_inline int > i40e_tx_free_bufs(struct i40e_tx_queue *txq) { > struct i40e_tx_entry *txep; > - uint16_t i; > + uint16_t tx_rs_thresh =3D txq->tx_rs_thresh; > + uint16_t i =3D 0, j =3D 0; > + struct rte_mbuf *free[RTE_I40E_TX_MAX_FREE_BUF_SZ]; > + const uint16_t k =3D RTE_ALIGN_FLOOR(tx_rs_thresh, > RTE_I40E_TX_MAX_FREE_BUF_SZ); > + const uint16_t m =3D tx_rs_thresh % RTE_I40E_TX_MAX_FREE_BUF_SZ; >=20 > if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz & > rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=3D >=20 > rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE)) > return 0; >=20 > - txep =3D &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]); > + txep =3D &txq->sw_ring[txq->tx_next_dd - (tx_rs_thresh - 1)]; >=20 > - for (i =3D 0; i < txq->tx_rs_thresh; i++) > + for (i =3D 0; i < tx_rs_thresh; i++) > rte_prefetch0((txep + i)->mbuf); >=20 > if (txq->offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE) { > - for (i =3D 0; i < txq->tx_rs_thresh; ++i, ++txep) { > - rte_mempool_put(txep->mbuf->pool, txep->mbuf); > - txep->mbuf =3D NULL; > + if (k) { > + for (j =3D 0; j !=3D k; j +=3D RTE_I40E_TX_MAX_FREE_BUF_SZ) > { > + for (i =3D 0; i < RTE_I40E_TX_MAX_FREE_BUF_SZ; > ++i, ++txep) { > + free[i] =3D txep->mbuf; > + txep->mbuf =3D NULL; > + } > + rte_mempool_put_bulk(free[0]->pool, (void > **)free, > + > RTE_I40E_TX_MAX_FREE_BUF_SZ); > + } > + } > + > + if (m) { > + for (i =3D 0; i < m; ++i, ++txep) { > + free[i] =3D txep->mbuf; > + txep->mbuf =3D NULL; > + } > + rte_mempool_put_bulk(free[0]->pool, (void **)free, > m); > } > } else { > for (i =3D 0; i < txq->tx_rs_thresh; ++i, ++txep) { > -- > 2.25.1 Acked-by: Beilei Xing