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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: MN2PR11MB3807.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 2aa62ee6-a291-4c8d-f214-08d926fd8e1b X-MS-Exchange-CrossTenant-originalarrivaltime: 04 Jun 2021 02:07:50.1054 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: cLP7sm6D4s2rZgnUnG4yYtKV9StIEnOdPypEkgpmfOhv3cJy0PS5Li9orSogANkj3zQaRl6/E/2kJbf6FQoP5A== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR11MB3791 X-OriginatorOrg: intel.com Subject: Re: [dpdk-dev] [PATCH v7 2/3] net/iavf: enable PCI bus master after reset X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions <dev.dpdk.org> List-Unsubscribe: <https://mails.dpdk.org/options/dev>, <mailto:dev-request@dpdk.org?subject=unsubscribe> List-Archive: <http://mails.dpdk.org/archives/dev/> List-Post: <mailto:dev@dpdk.org> List-Help: <mailto:dev-request@dpdk.org?subject=help> List-Subscribe: <https://mails.dpdk.org/listinfo/dev>, <mailto:dev-request@dpdk.org?subject=subscribe> Errors-To: dev-bounces@dpdk.org Sender: "dev" <dev-bounces@dpdk.org> > -----Original Message----- > From: Wang, Haiyue <haiyue.wang@intel.com> > Sent: Monday, May 24, 2021 9:24 AM > To: dev@dpdk.org > Cc: Zhang, Qi Z <qi.z.zhang@intel.com>; Wang, Liang-min <liang- > min.wang@intel.com>; david.marchand@redhat.com; Wang, Haiyue > <haiyue.wang@intel.com>; Wu, Jingjing <jingjing.wu@intel.com>; Xing, Beil= ei > <beilei.xing@intel.com> > Subject: [PATCH v7 2/3] net/iavf: enable PCI bus master after reset >=20 > The VF reset can be triggered by the PF reset event, then the PCI bus mas= ter > will be cleared, the VF will be not allowed to issue any Memory or I/O > Requests. >=20 > So after the reset event is detected, always enable the PCI bus master. > And if failed, the device or system may be in an invalid state, so keep t= he VF > reset state to mark it as I/O error. >=20 > Signed-off-by: Haiyue Wang <haiyue.wang@intel.com> > --- > drivers/net/iavf/iavf_ethdev.c | 10 +++++++++- > 1 file changed, 9 insertions(+), 1 deletion(-) >=20 > diff --git a/drivers/net/iavf/iavf_ethdev.c b/drivers/net/iavf/iavf_ethde= v.c > index d688c31cfb..a7ef7a6d4d 100644 > --- a/drivers/net/iavf/iavf_ethdev.c > +++ b/drivers/net/iavf/iavf_ethdev.c > @@ -2356,7 +2356,15 @@ iavf_dev_close(struct rte_eth_dev *dev) > rte_free(vf->aq_resp); > vf->aq_resp =3D NULL; >=20 > - vf->vf_reset =3D false; > + /* > + * If the VF is reset via VFLR, the device will be knocked out of bus > + * master mode, and the driver will fail to recover from the reset. Fix > + * this by enabling bus mastering after every reset. In a non-VFLR > case, > + * the bus master bit will not be disabled, and this call will have no > + * effect. > + */ > + if (vf->vf_reset && !rte_pci_set_bus_master(pci_dev, true)) > + vf->vf_reset =3D false; >=20 > return ret; > } > -- > 2.31.1 Acked-by: Beilei Xing <beilei.xing@intel.com>