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Wed, 11 Nov 2020 21:12:29 +0000 From: "Chen, Mike Ximing" To: "McDaniel, Timothy" CC: "dev@dpdk.org" , "Carrillo, Erik G" , "Eads, Gage" , "Van Haaren, Harry" , "jerinj@marvell.com" , "thomas@monjalon.net" , "david.marchand@redhat.com" Thread-Topic: [dpdk-dev] [PATCH] event/dlb2: add missing delayed token pop logic Thread-Index: AQHWuGmoiCVNstjGHUWkokzria6GgqnDa+7Q Date: Wed, 11 Nov 2020 21:12:29 +0000 Message-ID: References: <1605126422-522-1-git-send-email-timothy.mcdaniel@intel.com> In-Reply-To: <1605126422-522-1-git-send-email-timothy.mcdaniel@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-version: 11.5.1.3 dlp-reaction: no-action dlp-product: dlpe-windows authentication-results: intel.com; dkim=none (message not signed) header.d=none;intel.com; dmarc=none action=none header.from=intel.com; x-originating-ip: [69.141.167.85] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 3e3679de-b199-4b3d-4556-08d886867f84 x-ms-traffictypediagnostic: MN2PR11MB4583: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:88; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: MN2PR11MB4431.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 3e3679de-b199-4b3d-4556-08d886867f84 X-MS-Exchange-CrossTenant-originalarrivaltime: 11 Nov 2020 21:12:29.4910 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 12UBfgNed/CXzrvBaLYJkD++uuJOxtgsjqkdvj4mU49tSwUMYq0jZo/ndyygvTzivmtahALJL7GAoqEcj+H5vWBBE70qmx9jufgdTjVTeG0= X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR11MB4583 X-OriginatorOrg: intel.com Subject: Re: [dpdk-dev] [PATCH] event/dlb2: add missing delayed token pop logic X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" > -----Original Message----- > From: dev On Behalf Of Timothy McDaniel > Sent: Wednesday, November 11, 2020 3:27 PM > Cc: dev@dpdk.org; Carrillo, Erik G ; Eads, Gag= e > ; Van Haaren, Harry ; > jerinj@marvell.com; thomas@monjalon.net; david.marchand@redhat.com > Subject: [dpdk-dev] [PATCH] event/dlb2: add missing delayed token pop log= ic >=20 > The code contained in this commit was inadvertently omitted when dissecti= ng > the dlb2 code base into discrete patches for upstream. >=20 > Signed-off-by: Timothy McDaniel > --- > drivers/event/dlb2/dlb2.c | 314 +++++++++++++++++++++++--------= ------ > drivers/event/dlb2/dlb2_selftest.c | 4 +- > 2 files changed, 201 insertions(+), 117 deletions(-) >=20 > diff --git a/drivers/event/dlb2/dlb2.c b/drivers/event/dlb2/dlb2.c index > d42e48b..8672486 100644 > --- a/drivers/event/dlb2/dlb2.c > +++ b/drivers/event/dlb2/dlb2.c > @@ -1082,6 +1082,25 @@ dlb2_init_qe_mem(struct dlb2_port *qm_port, char > *mz_name) > return ret; > } >=20 > +static inline uint16_t > +dlb2_event_enqueue_delayed(void *event_port, > + const struct rte_event events[]); > + > +static inline uint16_t > +dlb2_event_enqueue_burst_delayed(void *event_port, > + const struct rte_event events[], > + uint16_t num); > + > +static inline uint16_t > +dlb2_event_enqueue_new_burst_delayed(void *event_port, > + const struct rte_event events[], > + uint16_t num); > + > +static inline uint16_t > +dlb2_event_enqueue_forward_burst_delayed(void *event_port, > + const struct rte_event events[], > + uint16_t num); > + > static int > dlb2_hw_create_ldb_port(struct dlb2_eventdev *dlb2, > struct dlb2_eventdev_port *ev_port, > @@ -1198,6 +1217,20 @@ dlb2_hw_create_ldb_port(struct dlb2_eventdev > *dlb2, >=20 > qm_port->dequeue_depth =3D dequeue_depth; > qm_port->token_pop_thresh =3D dequeue_depth; > + > + /* The default enqueue functions do not include delayed-pop support > for > + * performance reasons. > + */ > + if (qm_port->token_pop_mode =3D=3D DELAYED_POP) { > + dlb2->event_dev->enqueue =3D dlb2_event_enqueue_delayed; > + dlb2->event_dev->enqueue_burst =3D > + dlb2_event_enqueue_burst_delayed; > + dlb2->event_dev->enqueue_new_burst =3D > + dlb2_event_enqueue_new_burst_delayed; > + dlb2->event_dev->enqueue_forward_burst =3D > + dlb2_event_enqueue_forward_burst_delayed; > + } > + > qm_port->owed_tokens =3D 0; > qm_port->issued_releases =3D 0; >=20 > @@ -2427,11 +2460,6 @@ dlb2_event_build_hcws(struct dlb2_port *qm_port, > case 3: > case 2: > case 1: > - /* At least one QE will be valid, so only zero out three */ > - qe[1].cmd_byte =3D 0; > - qe[2].cmd_byte =3D 0; > - qe[3].cmd_byte =3D 0; > - > for (i =3D 0; i < num; i++) { > qe[i].cmd_byte =3D > cmd_byte_map[qm_port- > >is_directed][ev[i].op]; > @@ -2452,6 +2480,8 @@ dlb2_event_build_hcws(struct dlb2_port *qm_port, > qe[i].u.event_type.sub =3D ev[i].sub_event_type; > } > break; > + case 0: > + break; > } > } >=20 > @@ -2578,29 +2608,57 @@ dlb2_event_enqueue_prep(struct > dlb2_eventdev_port *ev_port, } >=20 > static inline uint16_t > -dlb2_event_enqueue_burst(void *event_port, > - const struct rte_event events[], > - uint16_t num) > +__dlb2_event_enqueue_burst(void *event_port, > + const struct rte_event events[], > + uint16_t num, > + bool use_delayed) > { > struct dlb2_eventdev_port *ev_port =3D event_port; > struct dlb2_port *qm_port =3D &ev_port->qm_port; > struct process_local_port_data *port_data; > - int i, cnt; > + int i; >=20 > RTE_ASSERT(ev_port->enq_configured); > RTE_ASSERT(events !=3D NULL); >=20 > - cnt =3D 0; > + i =3D 0; >=20 > port_data =3D &dlb2_port[qm_port->id][PORT_TYPE(qm_port)]; >=20 > - for (i =3D 0; i < num; i +=3D DLB2_NUM_QES_PER_CACHE_LINE) { > + while (i < num) { > uint8_t sched_types[DLB2_NUM_QES_PER_CACHE_LINE]; > uint8_t queue_ids[DLB2_NUM_QES_PER_CACHE_LINE]; > + int pop_offs =3D 0; > int j =3D 0; >=20 > + memset(qm_port->qe4, > + 0, > + DLB2_NUM_QES_PER_CACHE_LINE * > + sizeof(struct dlb2_enqueue_qe)); > + > for (; j < DLB2_NUM_QES_PER_CACHE_LINE && (i + j) < num; > j++) { > const struct rte_event *ev =3D &events[i + j]; > + int16_t thresh =3D qm_port->token_pop_thresh; > + > + if (use_delayed && > + qm_port->token_pop_mode =3D=3D DELAYED_POP && > + (ev->op =3D=3D RTE_EVENT_OP_FORWARD || > + ev->op =3D=3D RTE_EVENT_OP_RELEASE) && > + qm_port->issued_releases >=3D thresh - 1) { > + /* Insert the token pop QE and break out. This > + * may result in a partial HCW, but that is > + * simpler than supporting arbitrary QE > + * insertion. > + */ > + dlb2_construct_token_pop_qe(qm_port, j); > + > + /* Reset the releases for the next QE batch */ > + qm_port->issued_releases -=3D thresh; > + > + pop_offs =3D 1; > + j++; > + break; > + } >=20 > if (dlb2_event_enqueue_prep(ev_port, qm_port, ev, > &sched_types[j], > @@ -2611,38 +2669,52 @@ dlb2_event_enqueue_burst(void *event_port, > if (j =3D=3D 0) > break; >=20 > - dlb2_event_build_hcws(qm_port, &events[i], j, > + dlb2_event_build_hcws(qm_port, &events[i], j - pop_offs, > sched_types, queue_ids); >=20 > - if (qm_port->token_pop_mode =3D=3D DELAYED_POP && j < 4 && > - qm_port->issued_releases >=3D qm_port->token_pop_thresh - > 1) { > - dlb2_construct_token_pop_qe(qm_port, j); > - > - /* Reset the releases counter for the next QE batch */ > - qm_port->issued_releases -=3D qm_port- > >token_pop_thresh; > - } > - > dlb2_hw_do_enqueue(qm_port, i =3D=3D 0, port_data); >=20 > - cnt +=3D j; > + /* Don't include the token pop QE in the enqueue count */ > + i +=3D j - pop_offs; >=20 > - if (j < DLB2_NUM_QES_PER_CACHE_LINE) > + /* Don't interpret j < DLB2_NUM_... as out-of-credits if > + * pop_offs !=3D 0 > + */ > + if (j < DLB2_NUM_QES_PER_CACHE_LINE && pop_offs =3D=3D 0) > break; > } >=20 > - if (qm_port->token_pop_mode =3D=3D DELAYED_POP && > - qm_port->issued_releases >=3D qm_port->token_pop_thresh - 1) { > - dlb2_consume_qe_immediate(qm_port, qm_port- > >owed_tokens); > - qm_port->issued_releases -=3D qm_port->token_pop_thresh; > - } > - return cnt; > + return i; > +} > + > +static uint16_t > +dlb2_event_enqueue_burst(void *event_port, > + const struct rte_event events[], > + uint16_t num) > +{ > + return __dlb2_event_enqueue_burst(event_port, events, num, false); } > + > +static uint16_t > +dlb2_event_enqueue_burst_delayed(void *event_port, > + const struct rte_event events[], > + uint16_t num) > +{ > + return __dlb2_event_enqueue_burst(event_port, events, num, true); > } >=20 > static inline uint16_t > dlb2_event_enqueue(void *event_port, > const struct rte_event events[]) > { > - return dlb2_event_enqueue_burst(event_port, events, 1); > + return __dlb2_event_enqueue_burst(event_port, events, 1, false); } > + > +static inline uint16_t > +dlb2_event_enqueue_delayed(void *event_port, > + const struct rte_event events[]) > +{ > + return __dlb2_event_enqueue_burst(event_port, events, 1, true); > } >=20 > static uint16_t > @@ -2650,7 +2722,15 @@ dlb2_event_enqueue_new_burst(void *event_port, > const struct rte_event events[], > uint16_t num) > { > - return dlb2_event_enqueue_burst(event_port, events, num); > + return __dlb2_event_enqueue_burst(event_port, events, num, false); } > + > +static uint16_t > +dlb2_event_enqueue_new_burst_delayed(void *event_port, > + const struct rte_event events[], > + uint16_t num) > +{ > + return __dlb2_event_enqueue_burst(event_port, events, num, true); > } >=20 > static uint16_t > @@ -2658,7 +2738,93 @@ dlb2_event_enqueue_forward_burst(void > *event_port, > const struct rte_event events[], > uint16_t num) > { > - return dlb2_event_enqueue_burst(event_port, events, num); > + return __dlb2_event_enqueue_burst(event_port, events, num, false); } > + > +static uint16_t > +dlb2_event_enqueue_forward_burst_delayed(void *event_port, > + const struct rte_event events[], > + uint16_t num) > +{ > + return __dlb2_event_enqueue_burst(event_port, events, num, true); } > + > +static void > +dlb2_event_release(struct dlb2_eventdev *dlb2, > + uint8_t port_id, > + int n) > +{ > + struct process_local_port_data *port_data; > + struct dlb2_eventdev_port *ev_port; > + struct dlb2_port *qm_port; > + int i; > + > + if (port_id > dlb2->num_ports) { > + DLB2_LOG_ERR("Invalid port id %d in dlb2-event_release\n", > + port_id); > + rte_errno =3D -EINVAL; > + return; > + } > + > + ev_port =3D &dlb2->ev_ports[port_id]; > + qm_port =3D &ev_port->qm_port; > + port_data =3D &dlb2_port[qm_port->id][PORT_TYPE(qm_port)]; > + > + i =3D 0; > + > + if (qm_port->is_directed) { > + i =3D n; > + goto sw_credit_update; > + } > + > + while (i < n) { > + int pop_offs =3D 0; > + int j =3D 0; > + > + /* Zero-out QEs */ > + qm_port->qe4[0].cmd_byte =3D 0; > + qm_port->qe4[1].cmd_byte =3D 0; > + qm_port->qe4[2].cmd_byte =3D 0; > + qm_port->qe4[3].cmd_byte =3D 0; > + > + for (; j < DLB2_NUM_QES_PER_CACHE_LINE && (i + j) < n; j++) { > + int16_t thresh =3D qm_port->token_pop_thresh; > + > + if (qm_port->token_pop_mode =3D=3D DELAYED_POP && > + qm_port->issued_releases >=3D thresh - 1) { > + /* Insert the token pop QE */ > + dlb2_construct_token_pop_qe(qm_port, j); > + > + /* Reset the releases for the next QE batch */ > + qm_port->issued_releases -=3D thresh; > + > + pop_offs =3D 1; > + j++; > + break; > + } > + > + qm_port->qe4[j].cmd_byte =3D DLB2_COMP_CMD_BYTE; > + qm_port->issued_releases++; > + } > + > + dlb2_hw_do_enqueue(qm_port, i =3D=3D 0, port_data); > + > + /* Don't include the token pop QE in the release count */ > + i +=3D j - pop_offs; > + } > + > +sw_credit_update: > + /* each release returns one credit */ > + if (!ev_port->outstanding_releases) { > + DLB2_LOG_ERR("%s: Outstanding releases underflowed.\n", > + __func__); > + return; > + } > + ev_port->outstanding_releases -=3D i; > + ev_port->inflight_credits +=3D i; > + > + /* Replenish s/w credits if enough releases are performed */ > + dlb2_replenish_sw_credits(dlb2, ev_port); > } >=20 > static inline void > @@ -3067,86 +3233,6 @@ dlb2_inc_cq_idx(struct dlb2_port *qm_port, int cnt= ) > qm_port->gen_bit =3D (~(idx >> qm_port->gen_bit_shift)) & 0x1; } >=20 > -static int > -dlb2_event_release(struct dlb2_eventdev *dlb2, > - uint8_t port_id, > - int n) > -{ > - struct process_local_port_data *port_data; > - struct dlb2_eventdev_port *ev_port; > - struct dlb2_port *qm_port; > - int i, cnt; > - > - if (port_id > dlb2->num_ports) { > - DLB2_LOG_ERR("Invalid port id %d in dlb2-event_release\n", > - port_id); > - rte_errno =3D -EINVAL; > - return rte_errno; > - } > - > - ev_port =3D &dlb2->ev_ports[port_id]; > - qm_port =3D &ev_port->qm_port; > - port_data =3D &dlb2_port[qm_port->id][PORT_TYPE(qm_port)]; > - > - cnt =3D 0; > - > - if (qm_port->is_directed) { > - cnt =3D n; > - goto sw_credit_update; > - } > - > - for (i =3D 0; i < n; i +=3D DLB2_NUM_QES_PER_CACHE_LINE) { > - int j; > - > - /* Zero-out QEs */ > - qm_port->qe4[0].cmd_byte =3D 0; > - qm_port->qe4[1].cmd_byte =3D 0; > - qm_port->qe4[2].cmd_byte =3D 0; > - qm_port->qe4[3].cmd_byte =3D 0; > - > - for (j =3D 0; j < DLB2_NUM_QES_PER_CACHE_LINE && (i + j) < n; > j++) > - qm_port->qe4[j].cmd_byte =3D DLB2_COMP_CMD_BYTE; > - > - qm_port->issued_releases +=3D j; > - > - if (j =3D=3D 0) > - break; > - > - if (qm_port->token_pop_mode =3D=3D DELAYED_POP && j < 4 && > - qm_port->issued_releases >=3D qm_port->token_pop_thresh - > 1) { > - dlb2_construct_token_pop_qe(qm_port, j); > - > - /* Reset the releases counter for the next QE batch */ > - qm_port->issued_releases -=3D qm_port- > >token_pop_thresh; > - } > - > - dlb2_hw_do_enqueue(qm_port, i =3D=3D 0, port_data); > - > - cnt +=3D j; > - } > - > - if (qm_port->token_pop_mode =3D=3D DELAYED_POP && > - qm_port->issued_releases >=3D qm_port->token_pop_thresh - 1) { > - dlb2_consume_qe_immediate(qm_port, qm_port- > >owed_tokens); > - qm_port->issued_releases -=3D qm_port->token_pop_thresh; > - } > - > -sw_credit_update: > - /* each release returns one credit */ > - if (!ev_port->outstanding_releases) { > - DLB2_LOG_ERR("Unrecoverable application error. Outstanding > releases underflowed.\n"); > - rte_errno =3D -ENOTRECOVERABLE; > - return rte_errno; > - } > - > - ev_port->outstanding_releases -=3D cnt; > - ev_port->inflight_credits +=3D cnt; > - > - /* Replenish s/w credits if enough releases are performed */ > - dlb2_replenish_sw_credits(dlb2, ev_port); > - return 0; > -} > - > static inline int16_t > dlb2_hw_dequeue_sparse(struct dlb2_eventdev *dlb2, > struct dlb2_eventdev_port *ev_port, @@ -3367,8 +3453,7 > @@ dlb2_event_dequeue_burst(void *event_port, struct rte_event *ev, > uint16_t num, > if (ev_port->implicit_release && ev_port->outstanding_releases > 0) { > uint16_t out_rels =3D ev_port->outstanding_releases; >=20 > - if (dlb2_event_release(dlb2, ev_port->id, out_rels)) > - return 0; /* rte_errno is set */ > + dlb2_event_release(dlb2, ev_port->id, out_rels); >=20 > DLB2_INC_STAT(ev_port->stats.tx_implicit_rel, out_rels); > } > @@ -3405,8 +3490,7 @@ dlb2_event_dequeue_burst_sparse(void *event_port, > struct rte_event *ev, > if (ev_port->implicit_release && ev_port->outstanding_releases > 0) { > uint16_t out_rels =3D ev_port->outstanding_releases; >=20 > - if (dlb2_event_release(dlb2, ev_port->id, out_rels)) > - return 0; /* rte_errno is set */ > + dlb2_event_release(dlb2, ev_port->id, out_rels); >=20 > DLB2_INC_STAT(ev_port->stats.tx_implicit_rel, out_rels); > } > diff --git a/drivers/event/dlb2/dlb2_selftest.c > b/drivers/event/dlb2/dlb2_selftest.c > index f433654..5cf66c5 100644 > --- a/drivers/event/dlb2/dlb2_selftest.c > +++ b/drivers/event/dlb2/dlb2_selftest.c > @@ -1320,7 +1320,7 @@ test_delayed_pop(void) > } > } >=20 > - /* Dequeue dequeue_depth events but only release dequeue_depth - 2. > + /* Dequeue dequeue_depth events but only release dequeue_depth - 1. > * Delayed pop won't perform the pop and no more events will be > * scheduled. > */ > @@ -1336,7 +1336,7 @@ test_delayed_pop(void) >=20 > ev.op =3D RTE_EVENT_OP_RELEASE; >=20 > - for (i =3D 0; i < port_conf.dequeue_depth - 2; i++) { > + for (i =3D 0; i < port_conf.dequeue_depth - 1; i++) { > if (rte_event_enqueue_burst(evdev, 0, &ev, 1) !=3D 1) { > printf("%d: RELEASE enqueue expected to succeed\n", > __LINE__); > -- > 2.6.4 Looks good, and it fixed the delayed token pop issue in QA tests. Reviewed-by: Mike Ximing Chen